View MCM20027_5005135.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 1 imagemos imagemos advance information color sxga digital image sensor 1280 x 1024 pixel progressive scan solid state image sen- sor with integrated cds/pga/adc, digital programming, control, timing, and pixel correction features the MCM20027 is a fully integrated, high performance cmos image sensor with features such as integrated timing, control, and analog signal processing for digital imaging applications. the part provides designers a complete im- aging solution with a monolithic image capture and processing engine thus making it a true ?camera on a chip?. sys- tem benefits enable design of smaller, portable, low cost and low power systems. thereby making the product suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automo- tive among others. the imaging pixels are based on active cmos pixels using pinned photodiodes that are realized using motorola?s sub-micron imagemos tm technology. a maximum frame rate of 10 fps at full resolution can be achieved, further the frame rate is completely adjustable without adjusting the system clock. each pixel on the sensor is individually addressable allowing the user to control ?window of interest? (woi) panning and zooming. control of sub-sam- pling, resolution, exposure, gain, and other image processing features is accomplished via a two pin i 2 c interface. the sensor is run by supplying a single master clock. the sensor output is 10 digital bits providing wide dynamic range images. order this document by MCM20027/d MCM20027 1.3 megapixel this document contains information on a new product.specifications and information herein are subject to change with- out notice. features: ? sxga resolution, active cmos image sensor with square pixel unit cells ? 6.0 m m pitch pixels with patented pinned photodiode architecture ? bayer-rgb color filter array with optional micro lenses ? high sensitivity, quantum efficiency, and charge conversion efficiency ? low fixed pattern noise / wide dynamic range ? antiblooming and continuous variable speed shutter ? single master clock operation ? digitally programmable via i 2 c interface ? integrated on-chip timing/logic circuitry ? cds sample and hold for suppression of low frequency and correlated reset noise ? 20x programmable variable gain to optimize dynamic range and facilitate white balance and iris adjustment ? 10-bit, pipelined algorithmic rsd adc (dnl + 0.5 lsb, inl + 1.0 lsb) ? automatic column offset correction for noise suppression ? pixel addressability to support ?window of interest? windowing, resolution, and subsampling ? encoded data stream ? 10 fps full sxga at 13.5mhz master clock rate ? single 3.3v power supply ? 48 pin clcc package part number description package MCM20027ibbl color rgb sensor 48 pin clcc with lenslets MCM20027ibmn monochrome 48 pin clcc sensor without lenslets electro static discharge warning: this device is sensitive to electrostatic discharge (esd).esd immunity meets human body model (hbm) < 1500 v and machine model (mm) < 150 v additional esd data upon request. when handling this part, proper esd precautions should be followed to avoid exposing the de vice to dis- charges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime..
motorola revision 8.0 - 28 november 2001 : MCM20027 2 motorola semiconductor technical data imagemos imagemos specifications image size: 7.7mm x 6.1mm (9.82mm diagonal, 1/2? optic) resolution: 1280 x 1024 pixels, available digital zoom and region of interest (roi) windowing pixel size: 6 m m x 6 m m monochrome sensitivity: 1.8 v/lux-sec min. detectable light level: 3 lux at 10fps/f2 lens scan modes: progressive shutter modes: continuous frame and single frame rolling shutter modes available readout rate: 13.5msps frame rate: 0-10 full frames (1280x1024) per second max master clock frequency: 13.5mhz system dynamic range: 50db on chip programmable gain: -9.5db to 26db on chip image correction: column fixed pattern correction analog to digital converter: 10-bit, rsd adc (dnl +/-0.5 lsb, inl +/-1.0 lsb) power dissipation: 250mw rms, operating @13.5mhz package: 48 pin ceramic lcc temperature operating range: 0-40 o c figure 1. MCM20027 simplified block diagram sdata sclk 1280 x 1024 pixels (1296 x 1048 total including dark and isolation) c d s 10 bit adc post adc control signal i2c serial interface digital mclk init strobe sync adc(9:0) hclk vclk sof frc column offset white balance global gain global offset encoding control sensor interface
revision 8.0 - 28 november 2001 : MCM20027 motorola 3 motorola semiconductor technical data imagemos imagemos image sensor pixel array column decode, sensing, and muxing column sequencer & drivers column offset calibration color sequencer i 2 c serial interface i 2 c register decode column dova wb pga 0.88x - 2.84x global pga 0.696x - 7.48x global dova bandgap reference and bias generation 31 32 33 34 35 38 39 40 41 42 43 29 30 1 48 44 45 47 post adc processing test monitor logic 1280 1296 104 8 12dark +4isolation 4dark + 4isolation 4dark +4isolation 4da rk +4is olati on 1.5x 2.0x 6 6 6 6 analog switch 6 7 frame rate clamp 6 6 6 6 v refp v refm v cm i bias analog circuits digital logic 1 2 1 2 sof vclk hclk strobe clrca clrcb cvrefp extres adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 adc8 adc9 mclk sclk sdata init 10 bit rsd pipelined adc 10 10 10 11 ext_vinr ext_vins master row sequencer, integration control, and timing generator roe decoder and drivers 1024 15 cvrefm 14 20 19 16 17 18 21 extresrtn vag vagtrn vagref cvbg figure 2. MCM20027 detailed block diagram see ? MCM20027 pin definitions ? on page67 for more information
motorola revision 8.0 - 28 november 2001 : MCM20027 4 motorola semiconductor technical data imagemos imagemos table of contents 1.0 MCM20027 overview...................................................................... 7 2.0 MCM20027 architecture................................................................. 7 2.1 pixel architecture........................................................................... 7 2.2 color separation and fill factor enhancement .......................... 9 3.0 frame capture modes.................................................................... 10 3.1 continuous frame rolling shutter capture mode (default)........ 10 3.2 single frame rolling shutter capture mode (sfrs)................... 11 4.0 active window of interest control ................................................ 12 5.0 active window sub-sampling control.......................................... 12 6.0 frame rate and integration time control.................................... 13 6.1 cfrs frame time/rate:................................................................. 13 6.2 integration time in cfrs mode:................................................... 13 6.3 sfrs frame time/rate:................................................................. 14 6.4 integration time in sfrs mode.................................................... 14 6.5 example of frame time/rate and integration time in cfrs and sfrs modes.................................................................................... 7.0 analog signal processing chain overview ............................... 15 7.1 correlated double sampling (cds)............................................... 15 7.2 frame rate clamp (frc)................................................................ 15 7.3 programmable per-column offset .............................................. 16 7.4 digitally programmable gain amplifiers (dpga) for white bal- ance and exposure gain................................................................ 16 7.4.1 white balance control pga........................................................... 16 7.4.2 exposure global gain pga............................................................ 16 7.4.3 gain modes..................................................................................... 17 7.5 global digital offset voltage adjust (dova)................................ 19 7.6 analog to digital converter (adc)................................................ 19 8.0 MCM20027 sensor external controls........................................... 20 8.1 initialization .................................................................................... 20 8.2 standby mode............................................................................... 20
revision 8.0 - 28 november 2001 : MCM20027 motorola 5 motorola semiconductor technical data imagemos imagemos 8.3 tristate mode.................................................................................. 20 8.4 references cvrefp, cvrefm...................................................... 20 8.5 common mode references: vag, vagref and vagreturn. 20 8.6 internal bias current control......................................................... 21 9.0 sensor output/input signals......................................................... 22 9.1 start of data capture (sync)........................................................ 22 9.2 start of row readout (sof).......................................................... 22 9.3 horizontal data sync (vclk)........................................................ 22 9.4 data valid (hclk)........................................................................... 22 9.5 strobe signal................................................................................... 24 10.0 i 2 c serial interface.......................................................................... 26 10.1 MCM20027 i 2 c bus protocol ........................................................ 26 10.2 start signal.................................................................................. 26 10.3 slave address transmission......................................................... 26 10.4 acknowledgment ........................................................................... 26 10.5 data transfer.................................................................................. 26 10.6 stop signal...................................................................................... 27 10.7 repeated start signal................................................................. 27 10.8 i 2 c bus clocking and synchronization........................................ 27 10.9 register write................................................................................. 28 10.10 register read.................................................................................. 28 11.0 suggested software register changes........................................ 31 12.0 MCM20027 utility programming registers................................... 32 12.1 register reference map ................................................................ 32 13.0 detailed register block assignments.......................................... 35 14.0 electrical characteristics .............................................................. 64 15.0 MCM20027 pin definitions............................................................. 67 16.0 MCM20027 packaging information................................................ 69 17.0 MCM20027 typical electrical connection..................................... 72 table of contents
motorola revision 8.0 - 28 november 2001 : MCM20027 6 motorola semiconductor technical data imagemos imagemos reference documentation no description name of document release date contact/location of info 1 digital camera reference design utilizing the MCM20027 roadrunner application note may 4 2001 http://www.motorola.com/adc/imaging 2 information on MCM20027 optics optic application note feb 7 2001 http://www.motorola.com/adc/imaging 3 information on strobe timing strobe timing application note may 30 2001 http://www.motorola.com/adc/imaging table 1. reference documentation
revision 8.0 - 28 november 2001 : MCM20027 motorola 7 motorola semiconductor technical data imagemos imagemos 1.0 MCM20027 overview the MCM20027 is a solid state cmos active cmos imager (aci tm ) that integrates the functionality of a complete analog image acquisition, digitizer, and digital signal processing system on a single chip. the image sensor comprises a format pixel array with 1280x1024 active elements. the image size is fully programmable to user defined windows of interest. the pixels are on a 6.0 m m pitch. high sensitivity and low noise are a char- acteristic of the pinned ?shared diffusion? photodiode ar- chitecture utilized in the pixels. standard microlenses further enhance the sensitivity. the sensor is available with bayer patterned color filter arrays (cfas) for color output or as a monochrome imager. integrated timing and programming controls allow video or still image capture modes.frame rates are program- mable while keeping master clock frequency constant. user programmable row and column start/stop allow windowing to a minimum 1x1 pixel window (see ? active window of interest control ? on page12 ). windowing can also be performed by subsampling in multiple pixel increments to allow digital zoom (see ? active window sub-sampling control ? on page12 ). the analog video output of the pixel array is processed by an on chip analog signal processing pipeline. corre- lated double sampling (see ? correlated double sam- pling (cds) ? on page15 ) eliminates the sensor reset noise without the need to capture and subtract a reset frame per live video frame. the frame rate clamp (frc) enables real time optical black level calibration and offset correction (see ? frame rate clamp (frc) ? on page15 ). the programmable analog gain consists of exposure or global gain to map the signal swing to the adc input range, and white balance gain to perform col- or white balance in the analog domain. the asp signal chain consists of : (1) column op-amp(1.5x fixed gain) (2) column dova (1.5x fixed gain) (3) white balance pga (0.88-2.82x) (4) global pga (0.67x - 5.92x) (5) global dova (2.0x fixed gain) these digitally programmable amplifiers (dpgas) al- low real time color gain correction for auto white bal- ance (see ? white balance control pga ? on page16 ) as well as global gain adjustment (see ? exposure global gain pga ? on page16 ); offset calibration (see ? pro- grammable per-column offset ? on page16 and ? global digital offset voltage adjust (dova) ? on page19 ) can be done on a per column basis and globally. this per- column offset correction can be applied by using stored values in the on chip registers. a 10-bit redundant signed digit (rsd) adc converts the analog data to a 10-bit digital word stream. the fully differential analog signal processing pipeline serves to improve noise im- munity, signal to noise ratio, and system dynamic range. the sensor uses an industry standard two line i 2 c com- plaint serial interface. (see page 26 ). the MCM20027 operates with a single 3.3v power supply ( see ?electri- cal characteristics ? on page53 ) with no additional bias- es and requires only a single master clock for operation upto 13.5mhz. it is housed in a 48 pin ceramic lcc package (see ? MCM20027 packaging information ? on page69 ). the MCM20027 is designed taking into consideration interfacing requirements to standard video encoders. in addition to the 10 bit bayer encoded data stream, the sensor outputs the valid frame, line and pixel sync sig- nals needed for encoding. the sensor interfaces with a variety of commercially available video image proces- sors to allow encoding into various standard video for- mats. the MCM20027 is an elegant and extremely flexible single chip solution that simplifies a system designer?s tasks of image sensing, processing, digital conversion, and digital signal processing to a high performance, low cost, low power ic. one that supports among others a wide range of low power, portable consumer digital im- aging applications. 2.0 MCM20027 architecture 2.1 pixel architecture the MCM20027 imagemos tm ( 1 ) sensor comprises of a 1280 x 1024 active pixel array and supports progres- sive scan mode. the MCM20027 utilizes the kodak patented ?shared floating diffusion? pixel design 3 . this design enables two adjacent row pixels? photodiodes to share the same floating diffusion transistor. (see figure 2, on page8 ). 1. imagemos is a motorola trademark 2. patents held jointly by motorola and kodak 3. kodak patent pending
motorola revision 8.0 - 28 november 2001 : MCM20027 8 motorola semiconductor technical data imagemos imagemos the basic operation of the pixel relies on the photoelec- tric effect where due to its physical properties silicon is able to detect photons of light. the photons generate electron-hole pairs in direct proportion to the intensity and wavelength of the incident illumination. the appli- cation of an appropriate bias allows the user to collect the electrons and meter the charge in the form of a use- ful parameter such as voltage. the pixel architecture also requires all pixels in a row to have common reset , transfer 1 and 2, floating diffu- sion and row select gate controls. in addition all pixels have common supply (v dd ) and ground (v ss ) connec- tions. an optimized cell architecture provides enhance- ments such as noise reduction, fill factor maximizations, and antiblooming. the use of pinned photodiodes ( 2 ) and proprietary transfer gate devices in the photoele- ments enables enhanced sensitivity in the entire visual spectral range and a lag free operation. figure 2. shared floating diffusion pixel architecture how it works? in brief, initially during integration @t=0, both transfer gates 1 and 2 and the reset gate is open (on-active high). transfer gate 1 then closes (off) @ t=1, there- by allowing photodiode 1 to charge its well capacitance. at this time photodiode 2 is held at reset level by hav- ing transfer gate 2 and the reset gate open (on). af- ter 1 row period [t row ], @t=2 ,transfer gate 2 closes (off). this action causes photodiode 2 to start charging. when the integration (charging) of photdiode 1 has reset gate transfer gate 1 photodiode row 1 photodiode row2 transfer gate 2 shared floating diffusion gate row select gate transfer gate 1 transfer gate 2 reset gate row select gate shared floating diffusion gate t int t int t row t row t=0 t=1 t=2 t=4 t=5 t=6 t=3
revision 8.0 - 28 november 2001 : MCM20027 motorola 9 motorola semiconductor technical data imagemos imagemos neared completion, @ t=3, the reset gate closes (off). the charge off the well capacitance of photodiode 1 is then transfered to the shared floating diffusion gate @ t=4 when transfer gate 1 opens (on). also @t=4 the shared diffusion gate and the row select gate opens (on). this action causes charge from the floating diffusion to be read out as a voltage value for that pixel on row 1. @t=5 the row select gate and the floating diffusion close (off) while the reset gate opens (on). this is occurs in preparation of readout of row 2. when the integration (charging) of photodiode 2 has neared completion, the reset gate closes (off) again. the charge off the well capacitance of photodiode 2 is then transfered to the shared floating diffusion gate @ t=6 when transfer gate 2 opens (on) and then the same readout procedure as before occurs. the nominal photoresponse of the MCM20027 is shown in figure 3 figure 3. MCM20027 nominal spectral response in addition to the imaging pixels, there are additional pixels called dark and dummy pixels at the periphery of the imaging section (see figure 2 ). the dark pixels are covered by a light blocking shield rendering the pixels underneath insensitive to photons. these pixels provide the sensor means to measure the dark level offset which is used downstream in the signal processing chain to perform auto black level calibration. the dum- my pixels are provided at the array?s periphery to elimi- nate inexact measurements due to light piping into the dark pixels adjacent to active pixels. the output of these pixels should be discarded. electronic shuttering, also known as electronic expo- sure timing in photographic terms, is a standard feature. the pixel integration time can be widely varied from a small fraction of a given frame readout time to the entire frame time. 2.2 color separation and fill factor enhancement the MCM20027 family is offered with the option of monolithic polymer color filter arrays (cfas). the com- bination of an extremely planarized process and propri- atary color filter technology result in cfas with superior spectral and transmission properties. the standard op- tion is a primary (rgb) ?bayer? pattern (see figure 4 ), however, facility to produce customized cfas including complementary (cmyg) mosaics also exists. applications requiring higher sensitivity can benefit from the optional micro-lens arrays shown in figure 5 . the lenslet arrays can improve the fill factor (aperture ratio) of the sensor by 1.5-2x depending on the f number of the main lens used in the camera system. microlenses yield greatest benefits when the main lens has a high f number. as a caution, telecentric optical design is a re- quirement due to the limited optical acceptance angle of the lenslit. the optical acceptance angle is approxi- mately 15 degrees (see figure 5a). due to the lenslits being placed in the same area/position over all the pho- todiodes on the sensor, hence, care should be taken when taking into consideration the telecentric design for especially the outermost pixels.the fill factor of the pix- els without microlenses is 32%. with microlens the fill factor improves to approximately 45% to 50%. rgb srf, 400 to 1100nm -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400 500 600 700 800 900 1000 1100 wavelength, nm relative pixel response red pixels green-b pixels green-b pixels blue pixels
motorola revision 8.0 - 28 november 2001 : MCM20027 10 motorola semiconductor technical data imagemos imagemos figure 4. on-chip bayer cfa figure 5. a) 15 degrees acceptance angle b)improvement in pixel sensitivity results from fo- cusing incident light on photo sensitive portions of the pixel by using microlenses 3.0 frame capture modes there exists two frame capture modes: 1) continuous frame rolling shutter mode (cfrs) 2) single frame rolling shutter mode (sfrs) the sensor can be put into either one of the aforemen- tioned modes by writing either ?1? or ?0? to bit 6 of cap- ture mode control register , (table 29), on page 48 . 3.1 continuous frame rolling shutter capture (cfrs) [default] the default mode of image capture is the ?continuous frame rolling shutter? capture mode (cfrs). this mode will yield frame rates up to 10fps at 13.5 mhz mclk. in this mode the image integration and row read- out take place in parallel. while a row of pixels is being read out, another row(s) are being integrated. readout of each row follows the integration of that row. there- fore the integration of the rows are staggered out due to the readout of sequential rows occurring one after the other (see ? integration time in cfrs mode: ? on page13 ). in cfrs, after one frame has completed integrating, the first row of the second frame automatically begins integrating. the readout of the rows also follow the same routine. the waveforms depicting the cfrs out- put data stream refer to figure 6, on page11 and figure 7, on page12 . 3.1.1 cfrs video encoded data stream the pixel data stream signal control register , (table 53), on page 62 allows the user to select how the output pixel data stream in continuous frame rolling shutter mode is encoded/formatted. in default mode, internally generated signals sof, vclk, hclk etc. drive the in- tegration and readout of the pixel data frames but only the valid pixel data is readout of the sensor. when a ?1? is written to bit 5 of the pixel data stream signal control register , (table 53), on page 62 , it causes the output pixel data to be encoded with sof, vclk and end of frame signals. it accomplishes this by attaching the pix- el data with certain predefined signal data. the video encoded signal definitions , (table 2), on page 10 de- fines the data that represents the sof, vclk and end of frame signals. r r r r g1 g1 g1 g1 g2 g2 g2 b b b b g2 b b iris microlenses 15 o 15 o a b signal description data sof start of row read- out (i.e.. readout of row 1) 3ff3ff3ff3ff vclk start of row read- out of rows 2+ 3ff3ff000000 end of frame readout of last row complete 000000000000 table 2. video encoded signal definitions
revision 8.0 - 28 november 2001 : MCM20027 motorola 11 motorola semiconductor technical data imagemos imagemos 3.2 single frame rolling shutter capture mode (sfrs) this mode of capture refers to non-interlaced or se- quential row by row scanning of the entire sensor in a single pass for the purpose of capturing a single frame. the start of integration in this mode is triggered by the sync signal. similar to the cfrs capture mode, read- out of each row follows the integration of that row. therefore the integration of the rows are staggered out as well due to the readout of the sequential rows occur- ring one after the other (see ? integration time in sfrs mode ? on page14 ). this process continues until all rows have been integrated and readout. once readout of the entire frame is complete, the sensor awaits a new sync signal before it starts integration and readout of another frame. the waveforms depicting the sfrs output data stream refer to figure 8, on page12 note!! the faster the clock speed , the closer the se- quential integration start times are. figure 6. cfrs default frame waveform r o w 1 6 r o w 1 7 r o w 1 8 r o w 1 9 r o w 1 0 3 7 r o w 1 0 3 8 r o w 1 0 3 9 r o w 1 6 r o w 1 7 r o w 1 8 r o w 1 9 r o w 1 0 3 7 r o w 1 0 3 8 r o w 1 0 3 9 frame time = 1064 row times row time = 1338 mclks woi = 1280 columns x 1024 rows starting at row 16, column 8 sof vclk hclk blank 1 2 3 7 8 1 2 3 3 1 3 2 4 5 6 1 2 3 1 4 1 5 c o l . 9 c o l . 1 0 c o l . 1 2 8 6 c o l . 1 2 8 7 row 16 row 17 row time = vcw d + 39 1 2 3 1 0 5 1 0 6 valid pixel data adc[9:0] hclk vclk sof mclk pixel array values c o l . 8
motorola revision 8.0 - 28 november 2001 : MCM20027 12 motorola semiconductor technical data imagemos imagemos figure 7. cfrs default line waveform figure 8. sfrs waveform 4.0 active window of interest control the pixel data to be read out of the device is defined as a ?window of interest? (woi). the window of interest can be defined anywhere on the pixel array at any size. the user provides the upper-left pixel location and the size in both row and column depth to define the woi. the woi is defined using the woi pointer, woi depth, and woi width registers, ( table 32 on page 51 through table 39 on page 53 ). please refer to figure 9 for a pic- torial representation of the woi within the active pixel array. figure 9. woi definition 5.0 active window sub-sampling control the user can further control the size of the active win- dow that is read out by sub sampling the already de- fined active window of interest (see ? active window of interest control ? on page12 ). subsampling enables the pixel data to be readout in 1 pixel or 2 pixel increments depending if you are subsampling in either mono- chrome (1 pixel) or bayer pixel (2 pixel) space in four dif- ferent sampling rates in each direction: full, 1/2, 1/4, or 1/8. the user controls the subsampling via the sub- sample control register , (table 30), on page 49 . an example of bayer space sub-sampling is shown in figure 10 . figure 10. bayer space sub-sampling example r o w 1 6 r o w 1 7 r o w 1 8 r o w 1 9 r o w 1 0 3 7 r o w 1 0 3 8 r o w 1 0 3 9 sof vclk hclk sync t = (cint d + 1) * row time standard frame timing (figure 18) 0 1295 0 1047 woi pointer (wcp,wrp) w o i r o w d e p t h ( w r d ) woi column width (wcw) active pixel array window of interest (woi) sub-sample control register = x0 0 10101 b = progressive scan bayer pattern read 1 pattern, skip 1 pattern in both directions r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b
revision 8.0 - 28 november 2001 : MCM20027 motorola 13 motorola semiconductor technical data imagemos imagemos 6.0 frame rate and integration time control in addition to the minimum time required to readout the selected resolution and woi, the user has the ability to control the frame rates while operating in either contin- uous frame rolling shutter capture mode (cfrs) and single frame rolling shutter (sfrs). the frame rate can be defined as the time required to readout an entire frame of data plus the required bound- ary timing. this is done by varying the size of a number of parameters identified in later sections, the main one being the virtual frame surrounding the woi. please refer to figure 11 for a pictorial description of the virtual frame and its relationship to the woi . figure 11. virtual frame definition 6.1 cfrs frame time/rate: in continuous frame rolling shutter capture mode, the frame time is completely defined by the size of the vir- tual frame and can be expressed as: frame time = t frame = (vrd d + 1) * t row where vrd d defines the number of rows in the virtual frame. the user controls vrd d via the virtual frame row depth registers ( table 42 on page 55 and table 43 on page 55 ). frame rate = (frame time) -1 6.2 integration time in cfrs mode: in continuous frame rolling shutter capture mode, the integration time is defined as: integration time=t int = (cint d + 1) * t row where cint d is the number of virtual row times desired for integration time. therefore, the integration time in cfrs mode can be adjusted in steps of virtual frame row times.the user controls cint d via the integration time msb register , (table 40), on page 54 and inte- gration time lsb register , (table 41), on page 55 . row time (t row ) is the length of time required to read one row of the virtual frame and can be defined as: t row = (vcw d + shs d + shr d + 19) * mclk period where vcw d defines the number of columns in the virtu- al frame and shs d and shr d are internal timing control registers. the user controls vcw d via the cfrs virtual frame column width registers ( table 44 on page 56 and table 45 on page 56 ). the user controls the shs d and shr d values via the in- ternal timing control register 1 (shs time definition) ; table 50 and table51, ? internal timing control regis- ter 2 (shr time definition) ,? on page60 . note!! in continuous frame rolling shutter (cfrs) capture mode, the integration time upper limit is bounded by the frame time (see ? cfrs frame time/rate: ? on page13 ) . i.e.. t int < t frame 0 vcw[13:0] 0 vrd[13:0] woi pointer (wcp,wrp) w o i r o w d e p t h ( w r d ) woi column width (wcw) virtual frame window of interest (woi)
motorola revision 8.0 - 28 november 2001 : MCM20027 14 motorola semiconductor technical data imagemos imagemos 6.3 sfrs frame time/rate: in single frame rolling shutter capture mode the frame time is defined as: frame time = t frame = integration time+readout time readout time is the amount of time to readout the data af- ter integration of the row has been completed. it is defined as follows: readout time = (vrd d + 1) * t row where vrd d defines the number of rows in the virtual frame. the user controls vrd d via the cfrs virtual frame row depth registers ( table 42 on page 55 and table 43 on page 55 ). t row = (vcw d + shs d + shr d + 19) * mclk period for integration time see ? integration time in sfrs mode ? on page14 6.3.1 integration time in sfrs mode the integration time in single frame rolling shutter cap- ture mode is the same as in rolling shutter capture mode. for further information, see ? integration time in cfrs mode: ? on page13 . t he only difference is that in this mode the integration time is not bounded by the frame time 6.4 example of frame time/rate and integration time in cfrs and sfrs modes the following illustrates how to determine the frame time/ rate and integration time in both capture modes: assumptions: 1) active window of interest = 1280 x 1024 i.e.. (wcw d )=1279 ( wrd d )=1023 2) virtual column width ( vcw d )= 1290 3) virtual row depth ( vrd d ) = 1034 4) sample & hold time ( shs d ) = 10 5) sample & hold time ( shr d ) = 10 6) integration time ( cint d )= 350 7) mclk = 13.5 mhz note!! vcw d and cint d are typically varied frame to frame calculations: row time =trow = (vcwd + shsd + shrd + 19) = (1290 + 10 + 10 + 19) / 13.5e6 = 98.44 m s integration time = (cintd + 1) * trow =(350+1)*98.44 m s =34.5ms readout time = (vrdd + 1) * trow = frame time in cfrs mode frame time in cfrs mode = (vrd d + 1) * trow t frame =(1034 + 1)* 98.44 = 101.34 ms frame time in sfrs mode = t frame = integration time+readout time = 34.5ms + 101.34ms = 135.84ms results note!! cfrs integration time = 34.5ms because: t int < t frame = (vrd d + 1) * t row (see ? integration time in cfrs mode: ? on page13 ) capture mode t int t frame cfrs 34.5ms 101.34 ms sfrs 34.5ms 135.84ms
revision 8.0 - 28 november 2001 : MCM20027 motorola 15 motorola semiconductor technical data imagemos imagemos 7.0 analog signal processing chain overview the MCM20027?s analog signal processing (asp) chain incorporates correlated double sampling (cds), frame rate clamp (frc), two digitally programmable gain amplifiers (dpga), offset correction (dova), and a 10-bit analog to digital converter (adc). to see a pictorial depiction of this chain refer to ? speci- fications ? on page2 7.1 correlated double sampling (cds) the uncertainty associated with the reset action of a ca- pacitive node results in a reset noise which is equal to ktc; c being the capacitance of the node, t the temper- ature and k the boltzmann constant. a common way of eliminating this noise source in all image sensors is to use correlated double sampling. the output signal is sampled twice, once for its reset (reference) level and once for the actual video signal. these values are sam- pled and held while a difference amplifier subtracts the reference level from the signal output. double sampling of the signal eliminates correlated noise sources (see . ? conceptual block diagram of cds implementation. ? on page15 ) figure 12. conceptual block diagram of cds implementation. 7.2 frame rate clamp (frc) the frc ( figure 13 ) is designed to provide a feed for- ward dark level subtract reference level measurement. in the automatic frc mode, the optical black level ref- erence is re-established each time the image sensor begins a new frame. the MCM20027 uses optical black (dark) pixels to aid in establishing this reference. figure 13. frc conceptual block diagram on the MCM20027, dark pixel input signals should be sampled for a minimum of 137 m s to allow the two 0.1 m f capacitors at the clrca and clrcb pins sufficient time to charge for 10-bit accuracy. this guarantees that the frc?s ?droop? will be maintained at < 750 m v , thus assuring the specified adc 10-bit accuracy at + 0.5 lsb. therefore, at maximum operational frequency (13.5 mhz), the imager would require a number of frames to establish the dark pixel reference for subse- quent active pixel processing. the dark pixel sample period is automatically controlled internally and it is set to skip the first 3 dark rows and then sample the next 2 dark rows. when ?dark clamping? is active, each dark pixel is processed and held to establish pixel reference level at the clrca and clrcb pins. during this period, the frc?s differential outputs (v+ and v- on the diff amp, figure 13 ) are clamped to v cm . together, these actions help to eliminate the dark level offset, simulta- neously establishing the desired zero code at the adc output. care should be exercised in choosing the capacitors for the clrca, b pins to reflect different frame rates. the user can disable this function via the frc definition register ; table 54 and the power configuration regis- ter , (table 19), on page 41 (check this - should be re- ferring o frc clamp on/off) which will allow the asp chain to drift in offset per-column digital offset voltage adjust (dova), and controls the number of rows to clamp on. amp s/h1 s/h2 cdsp1 cdsp2 avin v+ v- + - v+ buf 1x frc v cm clrca cap lrca 0.1 m f lrclmp lrclmp + - buf 1x clrcb cap lrcb 0.1 m f lrclmp lrclmp previous + - diff amp v- v cm lrclmp v cm lrclmp stage
motorola revision 8.0 - 28 november 2001 : MCM20027 16 motorola semiconductor technical data imagemos imagemos 7.3 programmable per-column offset a programmable per-column offset adjustment is avail- able on the MCM20027. in order to reduce the risk and have the ability to cover any mode of repetitive column fixed pattern noise (fpn), there exists 64 registers that can be programmed with a dc offset that is added to all columns. ( mod64 column offset registers ; table 27 ). each register is 6 bits, (5 bits plus 1 sign bit), providing+/ - 32 register values. the dc register values is added to each of the 64 columns registers to provide the total off- set value. this set of 64 values is then repeatedly ap- plied to each bank of 64 in the sensor via the column dova stage of the asp chain. the column dova dc register ; table 26 , is used to set the initial offset of the pixel output in a range that will facilitate per-column offset data generation for varying operational conditions. in most operational scenarios, this register can be left in its default state of 00 h . this is a pre-image processing gain in comparison to the glo- bal dova register ( see section )which is a post image processing chain gain (pre a2d gain) 7.4 digitally programmable gain amplifiers (dpga) for white balance and exposure gain two dpgas are available in the analog signal process- ing chain. these are used to perform white balance and exposure gain functions. 7.4.1 white balance control pga the sensor produces three primary color outputs, red, green and blue. these are monochrome signals that represent luminance values in each of the primary col- ors. when added in equal amounts they mix to make neutral color. white balancing is a technique where the gain coefficients of the green(0), red, blue, and green(3) pixels comprising the bayer pattern (see figure 14 .) are set so as to equalize their outputs for neutral color scenes. since the sensitivity of the two green pixels in the bayer pattern may not be equal, an individual color gain register is provided for each component of the bay- er pattern. once all color gain registers are loaded with the desired gain coefficients ,according to which gain mode (see ? gain modes ? on page17 ) has been set, white balance is then achieved in real time and in analog space. these gain coefficient values are then selected and applied to the pixel output via a high speed path, the delay of which is much shorter than the pixel clock rate. real time updates can be performed to any of the gain regis- ters. however, latency associated with the i 2 c interface should be taken into consideration before changes oc- cur. in most applications, users will be able to assign predefined settings such as daylight, fluorescent, tung- sten, and halogen to cover a wide gamut of illumination conditions. both dpga designs use switched capacitors to mini- mize accumulated offset and improve measurement ac- curacy and dynamic range. the white balance gain registers are 6-bits and can be programmed to allow gain of 0.696x to 2.74x in varying steps. the user programs the individual gain coefficients into the MCM20027 via the color gain registers ( table 8 through table 11 ). for the default bayer configuration of the color filter array; figure 4 , the color gain register addresses are as follows: reg (00h): green pixel of a green-red row; reg (01h): red pixel; reg (02h): blue pix- el; and reg (03h): green pixel of a blue-green row. the MCM20027 is presently available with only a bayer cfa, however, it is designed to support other novel col- or configurations. this is accomplished via the color tile configuration register , (table 12), on page 37 and the color tile row definition registers ( table 13 through table 16 ). figure 14. color gain register selection 7.4.2 exposure global gain pga the global gain dpga provides a 0.67x to 7.5x (approx) programmable gain adjustment for dynamic range. the gain of the amplifier is linearly programmable using a six bit gain coefficients on 2 6-bit pga gain registers in varying steps depending on which exposure gain mode it is set at i.e. raw or lin or lin2 ( pga gain mode , (table 25), on page 45 ) . the user programs the global gain via the exposure pga global gain register a , (ta- ble 23), on page 44 . 6 6 dpga 6 6 6 green (0) red (1) blue (2) green (3) 0.7x-27x r(1) g(0) g(3) b(2)
revision 8.0 - 28 november 2001 : MCM20027 motorola 17 motorola semiconductor technical data imagemos imagemos 7.4.3 gain modes there exists different gain modes that are available when the sensor is performing white balance and ex- posure gain. the gain mode utilized for white balance and exposure gain can be selected by the user writing different values to the register described in table25, ? pga gain mode ,? on page45 . there are two different gain modes for white balance and there are three different gain modes for the expo- sure gain refer to white balance gain modes and gain formulas ; table 3 and exposure gain modes and gain formulas ; table 4 for more info. note!! the diagrams above illustrates how the color gain registers apply the gain onto each individual color pixel data: register no register name variable gain modes gain steps gain formula gain range 00h dpga color 1 gain register ; table 8 cg1 raw 0-32 0.6956 + (0.02174* cg1 d ) 0.69-1.39 33-63 1.391+ (0.0434* (cg1 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x cg1 d ) 0.69-2.74 01h dpga color 2 gain register ; table 9 cg2 raw 0-32 0.6956 + (0.02174* cg2 d ) 0.69-1.39 33-63 1.391+ (0.0434* (cg2 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x cg2 d ) 0.69-2.74 02h dpga color 3 gain register ; table 10 cg3 raw 0-32 0.6956 + (0.02174* cg3 d ) 0.69-1.39 33-63 1.391+ (0.0434* (cg3 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x cg3 d ) 0.69-2.74 03h dpga color 4 gain register ; table 11 cg4 raw 0-32 0.6956 + (0.02174* cg4 d ) 0.69-1.39 33-63 1.391+ (0.0434* (cg4 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x cg4 d ) 0.69-2.74 table 3. white balance gain modes and gain formulas green-red pixel data dpga color 1 gain register red pixel data dpga color 2 gain register blue pixel data dpga color 3 gain register green-blue pixel data dpga color 4 gain register
motorola revision 8.0 - 28 november 2001 : MCM20027 18 motorola semiconductor technical data imagemos imagemos register no register name variable gain modes gain steps gain formula gain range 10h exposure pga global gain register a ; table 23 gg1 raw 0-32 0.6956 + (0.02174* gg1 d ) 0.69-1.39 33-63 1.391+ (0.0434* (gg1 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x gg1 d ) 0.69-2.74 linear 2 0-67 0.6956 + (0.0434 * gg2 d ) 0.69-3.60 21h exposure pga global gain register b ; table 24 gg2 raw 0-32 0.6956 + (0.02174* cg2 d ) 0.69-1.39 33-63 1.391+ (0.0434* (cg2 d -32) 1.39-2.74 linear 0-47 0.6956 +(0.0434 x cg2 d ) 0.69-2.74 linear 2 0-67 0.6956 + (0.0434 * gg2 d ) 0.69-3.60 table 4. exposure gain modes and gain formulas the diagram below illustrates how the exposure gain registers apply the gain onto the pixel data: pixel data exposure pga gain register a exposure pga gain register b
revision 8.0 - 28 november 2001 : MCM20027 motorola 19 motorola semiconductor technical data imagemos imagemos 7.5 global digital offset voltage adjust (dova) a programmable global offset adjustment is available on the MCM20027. a user defined offset value is loaded via a 6-bit signed magnitude programming code via the global dova register , (table 28), on page 47 . offset correction allows fine-tuning of the signal to re- move any additional residual error which may have ac- cumulated in the analog signal path. this function is performed directly before analog to digital conversion and introduces a fixed gain of 2.0x. this feature is use- ful in applications that need to insert a desired offset to adjust for a known system noise floor relative to avss and offsets of amplifiers in the analog chain. 7.6 analog to digital converter (adc) the adc is a fully differential, low power circuit. a pipe- lined, redundant signed digit (rsd) algorithmic tech- nique is used to yield an adc with superior characteristics for imaging applications. integral noise linearity (inl) and differential noise lin- earity (dnl) performance is specified at + 1.0 and + 0.5, respectively, with no missing codes. the input voltage resolution is 2.44 mv with a full-scale 2.5 v pp input (2.5 v pp /2 10 ). the input dynamic range of the adc is pro- grammed via a programmable voltage reference gen- erator. the positive reference voltage (vrefp) and negative reference voltages (vrefm) can be pro- grammed from 2.5v to 1.25v and 0v to 1.25v respec- tively in steps of 5mv via the reference voltage registers ( table 17 and table 18 ). this feature is used independently or in conjunction with the dpgas to max- imize the system dynamic range based on incident illu- mination. the default input range for the adc is 1.9v for vrefp and 0.6v for vrefm hence allowing a 10 bit digitization of a 1.3v peak to peak signal.
motorola revision 8.0 - 28 november 2001 : MCM20027 20 motorola semiconductor technical data imagemos imagemos 8.0 sensor external controls (additional operational conditions) the MCM20027 includes initialization, standby modes, and external reference voltage outputs to afford the user additional applications flexibility. 8.1 initialization the init input pin (#42) controls reinitialization of the MCM20027. this serves to assure controlled chip and system startup. control is asserted via a logic high in- put. (i.e.. asserting a logic high ?1? initializes all the registers, while asserting a logic low ?0? returns the sensor to normal operation). this state must be held a minimum of 1 ms and a 1 ms ?wait period? should be al- lowed before chip processing to ensure that the start-up routines within the MCM20027 have run to completion, and to guarantee that all holding and bypass capacitors, etc. have achieved their required steady state values. tasks which are accomplished during startup include: reset of the utility programming registers and initializa- tion to their default values (please refer to previous sec- tion for settings), reset of all internal counters and latches, and setup of the analog signal processing chain. another method of saving power consumption is to ap- plying an active high signal to the init pin (#42) but note - doing this will also cause initialization of the chip . 8.2 standby mode the standby mode option is implemented to allow the user to reduce system power consumption during peri- ods which do not require operation of the MCM20027. this feature allows the user to extend battery life in low power applications. by utilizing this mode, the user may reduce dynamic power consumption from 250mw rms nominal @13.5mhz to < 100 uw in the standby mode. the standby mode is activated by writing a ?1? to bit 0 of ? power configuration register ? on page41 . writing a ?0? restores normal operation. 8.3 tristate mode the sensors hclk, sof, vclk, sync and strobe output signals as well as the pixel output data can be tristated via the tristate control register , (table 21), on page 42 . 8.4 references cvrefp, cvrefm the MCM20027 contains all internally generated refer- ences and biases on-chip for system simplification. an internally generated differential bandgap regulator de- rives all the adc and other analog signal processing re- quired references. the user should connect 0.1 m f capacitors to the cvrefp and cvrefm pins (#15 and #14 respectively) to accurately hold the biases. 8.5 common mode references: vag, vagref and vagreturn the MCM20027 holds the common mode reference voltages on the chip to a stable value. in order to achieve this stable value, the vag (pin #16), vagref(pin #18 ) and vagreturn (pin #17) have to be connected to two 0.1 m f capacitors in the manner de- scribed in the diagram below: 0.1 m f 0.1 m f vag (pin #16) vagreturn (pin #17) vagref (pin #18)
revision 8.0 - 28 november 2001 : MCM20027 motorola 21 motorola semiconductor technical data imagemos imagemos 8.6 internal bias current control the asp chain has internally generated bias currents that result in an operating power consumption of nearly 400mw approx. (accurate value will be given upon sen- sor testing). by attaching a resistor between pin 20, ex- tres; and pin19, the user can reduce the power consumption of the device. this feature is enabled by writing a 1 b to bit res of the power configuration regis- ter . additional power savings can be achieved at lower clock rates. note - the external bias resistor input pin (extresp - pin #20) should be connected to the etresrtn (pin#19) in the manner described in the di- agram below. resistor extresp (pin #20) extresrtn (pin #19)
motorola revision 8.0 - 28 november 2001 : MCM20027 22 motorola semiconductor technical data imagemos imagemos 9.0 sensor output/input signals 9.1 start of data capture (sync) this signal is utilized by the sensor to indicate the start of integration (data capture) in single frame rolling shutter capture mode (sfrs). for more info refer to figure 15, on page22 , figure 8, on page12 and figure 16, on page24 . this signal can be generated internally by the sensor or be driven via pin # 46 of the sensor (see figure 20, on page67 ). to set whether the signal is generated internally or externally, as well as other settings to this signal, refer to sync and strobe control register , (table 31), on page 50 . 9.2 start of row readout (sof) this signal triggers/indicates the start of row readout of the frame. this signal is an output and can be read via pin # 48 of the sensor (see figure 20, on page67 ). the sof signal delay as well as its length can be set by the user via sof delay register , (table 46), on page 57 and sof & vclk signal length control register , (table 48), on page 57 . for timing diagrams depicting the use of the sof signal refer to figure 15, on page22 , figure 6, on page11 , figure 7, on page12 , figure 8, on page12 and figure 16, on page24 . 9.3 horizontal data sync (vclk) this signal triggers the readout of the sequential rows of the frame. this signal is an output and can be read via pin # 44 of the sensor (see figure 20, on page67 ). the vclk signal delay in relation to sof, as well as its length can be set by the user via vclk delay register , (table 47), on page 57 and sof & vclk signal length control register , (table 48), on page 57 . for timing di- agrams depicting the use of the vclk signal refer to fig- ure 15, on page22 , figure 6, on page11 , figure 7, on page12 , figure 8, on page12 and figure 16, on page24 . 9.4 data valid (hclk) this signal triggers/indicates a single active pixel data has been readout (eg column 5 of row 10 data has been read out). this signal is an output and can be read via pin # 45 of the sensor (see figure 20, on page67 ). the hclk signal delay can be set by the user via hclk delay register , (table 52), on page 60 . for timing diagrams depicting the use of the hclk signal refer to figure 15, on page22 , figure 6, on page11 , figure 7, on page12 ,and figure 8, on page12 . figure 15. pixel data bus iinterface timing specifications (see table below) mclk sync t hsync t susync t dsof t dvclk sof vclk t drhclk hclk t dadc adc[9:0] t dfhclk
revision 8.0 - 28 november 2001 : MCM20027 motorola 23 motorola semiconductor technical data imagemos imagemos pixel data bus interface timing specifications (see figure 15 ) symbol characteristic min typ max unit f max mclk maximum frequency 1 11.5 13.5 mhz t hsync sync hold time w.r.t mclk 3.5 - 9 ns t susync sync setup time w.r.t mclk 3.0 - 8.5 ns t dsof mclk to sof delay time 8 13 21.5 ns t dvclk mclk to vclk delay time 8.5 13.5 22 ns t drhclk rising edge of mclk to rising edge of hclk delay time 7.5 13 22 ns t dfhclk falling edge of mclk to falling edge of hclk delay time 3 5 10.5 ns t dadc mclk to adc[9:0] delay time 8 13 21.5 ns t strobe mclk to strobe delay time 8 13 21.5 ns
motorola revision 8.0 - 28 november 2001 : MCM20027 24 motorola semiconductor technical data imagemos imagemos 9.5 strobe signal the strobe signal is a output pin on the MCM20027 sensor that can be used to activate ?flash/strobe illumi- nation modules?. it can be activated by writing a ?1? to bit 3 of ? sync and strobe control register ? on page50 while in sfrs mode. when activated, the strobe signal goes high (active) when all rows are integrating simul- taneously, and ends one row period ( t row) before the last row begins to integrate. (see 3 ? frame rate and in- tegration time control ? on page13 ). the start of the strobe signal can also be set by the user. in default mode, when the strobe is activated, the signal fires 2 row periods ( t row ) before the first row begins to read- out and last for a length of 1 t row .a sample timing dia- gram for the strobe signal can be seen in figure 16, on page24 : figure 16. strobe timing diagram in sfrs capture mode t int t int t int t int t row t row t row t row t row t row t frame t row t row sync last row of integration sof vclk strobe 3rd row of integration 2nd row of integration 1st row of integration t strobe2 t strobe1
revision 8.0 - 28 november 2001 : MCM20027 motorola 25 motorola semiconductor technical data imagemos imagemos to ensure that strobe signal fires, the integration time must be large enough to ensure that all rows are inte- grating simulanteously for at least 2 row periods ( t row ) (see ? frame rate and integration time control ? on page13 ) where t row = (vcw d + shs d + shr d + 19) to accomplish this - ensure that the integration time ( cint d ) greater than 2 row periods ( t row ) larger than the active window of interest row depth. min. integration time =t intmin = (cint min +1)* t row cint min =wrd d +x where x > 2 where wrd d is the window of interest row depth. t strobe1 = t row t strobe2 = t intmin - (wrd d +1)* t row example: below you will find an example of how to ensure that the strobe signal will fire and to determine the length of the strobe signal in default mode: (refer to figure 16, on page24 for timing analysis) goal (for example purpose): strobe signal that lasts for at least 250us, which is the length of a typical strobe/flash event. assumptions: 1) active window of interest = 1280 x 1024 ie. (wcw d )=1279 ( wrd d )=1023 2) virtual column width ( vcw d )= 1290 3) virtual row depth ( vrd d ) = 1034 4) sample & hold time ( shs d ) = 10 5) sample & hold time ( shr d ) = 10 6) mclk = 13 mhz variables: integration time ( cint min ) is the main variable used to control the time of the strobe signals. t intmin = (cint min +1)* t row calculations: row time =trow = (vcwd + shsd + shrd + 19) = (1290 + 10 + 10 + 19) / 13.5e6 = 98.44 m s t intmin = (cint min +1)* t row cint min =wrd d +x where x > 2 let cint min = wrd d +x where x > 2 = 1023 + 4 = 1029 where x=4 therefore, t intmin = 101.39 t strobe1 = 98.44 m s t strobe2 = t intmin - (wrd d +2)* t row = 3 * t row = 295us results : note!! refer to figure 16, on page24 for timing analysis signal value t row 98us t int 101ms t strobe1 98us t strobe2 295us t frame 202ms
motorola revision 8.0 - 28 november 2001 : MCM20027 26 motorola semiconductor technical data imagemos imagemos 10.0 i 2 c serial interface the i 2 c is an industry standard which is also compatible with the motorola bus (called m-bus) that is available on many microprocessor products. the i 2 c contains a se- rial two-wire half-duplex interface that features bidirec- tional operation, master or slave modes, and multi- master environment support. the clock frequency on the system is governed by the slowest device on the board. the sdata and sclk are the bidirectional data and clock pins, respectively. these pins are open drain and will require a pull-up resistor to vdd of 1.5 k w to 10 k w (see page66 ). the i 2 c is used to write the required user system data into the program control registers in the MCM20027. the i 2 c bus can also read the data in the program con- trol register for verification or test considerations. the MCM20027 is a slave only device that supports a max- imum clock rate (sclk) of 100 khz while reading or writing only one register address per i 2 c start/stop cy- cle. the following sections will be limited to the methods for writing and reading data into the MCM20027 regis- ter. for a complete reference to i 2 c, see ?the i 2 c bus from theory to practice? by dominique paret and carll- fenger, published by john wiley & sons, isbn 0471962686. 10.1 MCM20027 i 2 c bus protocol the MCM20027 uses the i 2 c bus to write or read one register byte per start/stop i 2 c cycle as shown in figure 17 and figure 18 . these figures will be used to describe the various parts of the i 2 c protocol communications as it applies to the MCM20027. MCM20027 i 2 c bus communication is basically com- posed of following parts: start signal, MCM20027 slave address (0110011 b ) transmission followed by a r/ w bit, an acknowledgment signal from the slave, 8 bit data transfer followed by another acknowledgment sig- nal, stop signal, repeated start signal, and clock synchronization. 10.2 start signal when the bus is free, i.e. no master device is engaging the bus (both sclk and sdata lines are at logical ?1?), a master may initiate communication by sending a start signal. as shown in figure 17 , a start signal is defined as a high-to-low transition of sdata while sclk is high. this signal denotes the beginning of a new data transfer and wakes up all the slaves on the bus. 10.3 slave address transmission the first byte of a data transfer, immediately after the start signal, is the slave address transmitted by the master. this is a 7-bit calling address followed by a r/ w bit. the seven-bit address for the MCM20027, start- ing with the msb (ad7) is 0110011 b . the transmitted calling address on the sdata line may only be changed while sclk is low as shown in figure 17 . the data on the sdata line is valid on the high to low sig- nal transition on the sclk line. the r/ w bit following the 7-bit tells the slave the desired direction of data transfer: ? 1 = read transfer, the slave transitions to a slave transmitter and sends the data to the master ? 0 = write transfer, the master transmits data to the slave 10.4 acknowledgment only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sdata line low at the 9th clock (see figure 17 ). if a transmitted slave address is acknowledged, successful slave addressing is said to have been achieved. no two slaves in the system may have the same address. the MCM20027 is configured to be a slave only. 10.5 data transfer once successful slave addressing is achieved, data transfer can proceed between the master and the se- lected slave in a direction specified by the r/ w bit sent by the calling master. note that for the first byte after a start signal (in figure 17 and figure 18 ), the r/ w bit is always a ?0? designating a write transfer. this is re- quired since the next data transfer will contain the reg- ister address to be read or written. all transfers that come after a calling address cycle are referred to as data transfers, even if they carry sub-ad- dress information for the slave device. each data byte is 8 bits long. data may be changed only while sclk is low and must be held stable while sclk is high as shown in figure 17 . there is one clock pulse on sclk for each data bit, the msb being transferred first. each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pull- ing the sdata low at the ninth clock. so one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sdata line must be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling.
revision 8.0 - 28 november 2001 : MCM20027 motorola 27 motorola semiconductor technical data imagemos imagemos if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sdata line for the master to generate stop or start signal. 10.6 stop signal the master can terminate the communication by gener- ating a stop signal to free the bus. however, the mas- ter may generate a start signal followed by a calling command without generating a stop signal first. this is called a repeated start. a stop signal is defined as a low-to-high transition of sdata while sclk is at logical ?1? (see figure 17 ). the master can generate a stop even if the slave has generated an acknowledge bit at which point the slave must release the bus. 10.7 repeated start signal a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. this is used by the master to commu- nicate with another slave or with the same slave in a dif- ferent mode (transmit/receive mode) without releasing the bus. as shown in figure 18 , a repeated start signal is be- ing used during the read cycle and to redirect the data transfer from a write cycle (master transmits the register address to the slave) to a read cycle (slave transmits the data from the designated register to the slave). figure 17. write cycle using i 2 c bus 10.8 i 2 c bus clocking and synchronization open drain outputs are used on the sclk outputs of all master and slave devices so that the clock can be syn- chronized and stretched using wire-and logic. this means that the slowest device will keep the bus from going faster than it is capable of receiving or transmit- ting data. after the master has driven sclk from high to low, all the slaves drive sclk low for the required period that is needed by each slave device and then releases the sclk bus. if the slave sclk low period is greater than the master sclk low period, the resulting sclk bus signal low period is stretched. therefore, synchronized clocking occurs since the sclk is held low by the de- vice with the longest low period. also, this method can be used by the slaves to slow down the bit rate of a transfer. the master controls the length of time that the sclk line is in the high state. the data on the sdatline is valid when the master switches the sclk line from a high to a low. slave devices may hold the sclk low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the sclk line. sclk 1 2 3 4 5 6 7 8 msb 1 2 3 4 5 6 7 8 msb lsb 9 9 1 2 3 4 5 6 7 8 msb lsb d7 d6 d5 d4 d3 d2 d1 d0 9 ack bit data to write MCM20027 register stop signal from MCM20027 sclk sdata sdata start signal ack bit ad7 ad6 ad5 ad4 ad3 ad2 ad1 d7 d6 d5 d4 d3 d2 d1 d0 MCM20027 i 2 c bus address MCM20027 register address write from MCM20027 ack bit from MCM20027 ?0? ?1? ?0? ?1? ?0? ?1? ?1? lsb
motorola revision 8.0 - 28 november 2001 : MCM20027 28 motorola semiconductor technical data imagemos imagemos 10.9 register write writing the MCM20027 registers is accomplished with the following i 2 c transactions (see figure 17 ): ? master transmits a start ? master transmits the MCM20027 slave calling ad- dress with ?write? indicated (byte=66 h , 102 d , 01100110 b ) ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock, if the call- ing address was received ? master transmits the MCM20027 register address ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock after re- ceiving the register address ? master transmits the data to be written into the reg- ister at the previously received register address ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock after re- ceiving the data to be written into the register address ? master transmits stop to end the write cycle 10.10 register read reading the MCM20027 registers is accomplished with the following i 2 c transactions (see figure 18 ): ? master transmits a start ? master transmits the MCM20027 slave calling ad- dress with ?write? indicated (byte=66 h , 102 d , 01100110 b ) ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock, if the calling address was received ? master transmits the MCM20027 register address ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock after receiv- ing the register address ? master transmits a repeated start ? master transmits the MCM20027 slave calling ad- dress with ?read? indicated (byte = 67 h, 103 d , 01100111 b ) ? MCM20027 slave sends acknowledgment by forc- ing the sdata low during the 9th clock, if the call- ing address was received ? at this point, the MCM20027 transitions from a ?slave-receiver? to a ?slave-transmitter? ? MCM20027 sends the sclk and the register data contained in the register address that was previ- ously received from the master; MCM20027 transi- tions to slave-receiver ? master does not send an acknowledgment (nak) ? master transmits stop to end the read cycle
revision 8.0 - 28 november 2001 : MCM20027 motorola 29 motorola semiconductor technical data imagemos imagemos figure 18. read cycle using i 2 c bus sclk sdata start signal ack bit 1 2 3 4 5 6 7 8 msb lsb 1 2 3 4 5 6 7 8 msb lsb 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 d7 d6 d5 d4 d3 d2 d1 d0 MCM20027 i 2 c bus address MCM20027 register address write from mcm20014 ack bit from MCM20027 xx repeated start signal 1 2 3 4 5 6 7 8 msb lsb 9 read sclk sdata 1 2 3 4 5 6 7 8 msb lsb d7 d6 d5 d4 d3 d2 d1 d0 9 data from MCM20027 register stop signal from master single byte transfer to master MCM20027 i 2 c bus address sclk sdata no ack. bit from master terminates the transfer ?0? ?1? ?0? ?1? ?0? ?1? ?1? ad7 ad6 ad5 ad4 ad3 ad2 ad1 ?0? ?1? ?0? ?1? ?0? ?1? ?1? ack bit fromMCM20027 at this point the MCM20027 transitions from a ?slave-receiver? to a ?slave- transmitter? the MCM20027 transitions from a ?slave-transmitter? to a ?slave-receiver? after the register data is sent
motorola revision 8.0 - 28 november 2001 : MCM20027 30 motorola semiconductor technical data imagemos imagemos figure 19. i 2 c serial interface 6 timing specifications i 2 c serial interface 6 timing specifications (see figure 19 ) symbol characteristic min max unit f max sclk maximum frequency 50 400 khz m1 start condition sclk hold time 4 - t mclk 7 m2 sclk low period 8 - t mclk m3 sclk/sdata rise time [from v il = (0.2)*vdd to v ih = (.8)*vdd] - .3 m s 8 m4 sdata hold time 4 - t mclk 7 m5 sclk/sdata fall time (from vh = 2.4v to vl = 0.5v) - .3 m s 8 m6 sclk high period 4 - t mclk m7 sdata setup time 4 - t mclk 7 m8 start / repeated start condition sclk setup time 4 - t mclk m9 stop condition sclk setup time 4 - t mclk c i capacitive for each i/o pin - 10 pf cbus capacitive bus load for sclk and sdata - 200 pf rp pull-up resistor on sclk and sdata 1.5 10 k w 9 6 i 2 c is a proprietary phillips interface bus 7 the unit t mclk is the period of the input master clock; the frequency of mclk is assumed 13.5 mhz 8 the capacitive load is 200 pf 9 a pull-up resistor to vdd is required on each of the sclk and sdata lines; for a maximum bus capacitive load of 200 pf, the min imum value of rp should be selected in order to meet specifications m1 sclk m3 m5 v ih v il m2 m6 sdata m4 m7 m8 m9 m8
revision 8.0 - 28 november 2001 : MCM20027 motorola 31 motorola semiconductor technical data imagemos imagemos 11.0 suggested software register programming reference there are number of registers whose default values we have been changed to make the sensor operational with a digital still camera. the registers, there suggested new values (changes) and reason for there change are detailed in suggested register default value changes , (table 5), on page 31 note!! these are only suggested value changes. de- pending on the application, there might exist more or less registers whose default values require modifica- tions. register no register name default values new values comment 0c h power configuration register ; table 19 00 h 08 h switching external resistor on for lower active power consumption 22 h pga gain mode ; table 25 00 h 06 h white balance switched from raw to linear gain mode . exposure gain switched from raw to linear 2 gain mode 23 h global dova register ; table 28 00 h 27 h negative offset for analog signal process- ing chain 42 h sync and strobe control register ; table 31 02 h 00 h necessary for switch to sfrs capture mode in addition to capture mode control register 56 h sof & vclk signal length control register ; table 48 0e h 09 h new sof = 64 mclks new vclk = 8 mclks 5f h internal timing control register 1 (shs time defi- nition) ; table 50 0a h 00 h new shs=64 mclks increase sample time to sweep all available charge from pixel 60 h internal timing control register 2 (shr time defini- tion) ; table 51 0a h 00 h new shr=64 mclks increased reset timesweep all available charge from pixel table 5. suggested register default value changes
motorola revision 8.0 - 28 november 2001 : MCM20027 32 motorola semiconductor technical data imagemos imagemos 12.0 MCM20027 utility programming registers 12.1 register reference map the i 2 c addressing is broken up into groups of 16 and assigned to a specific digital block. the designated block is responsible for driving the internal control bus, when the assigned range of addresses are present on the internal address bus. the grouping designation and assigned range are listed in table 6 . each block con- tains registers which are loaded and read by the digital and analog blocks to provide configuration control via the i 2 c serial interface. table 7 contains all the i 2 c address assignments. the table includes a column indicating whether the register values are shadowed with respect to the sensor inter- face. if the register is shadowed, the sensor interface will only be updated upon frame boundaries, thereby eliminating intraframe artifacts resulting from register changes. address range block name 00 h - 2f h analog register interface 40 h - 7f h sensor interface 80 h - bf h column offset coeff. table 6. i 2 c address range assignments hex address register function defa ult ref. table shadow ed? 00 h dpga color 1 gain register (green of green-red row) 0e h table 8, page 35 yes 01 h dpga color 2 gain register (red) 0e h table 9, page 35 yes 02 h dpga color 3 gain register (blue) 0e h table 10, page 36 yes 03 h dpga color 4 gain register (green of blue-green row) 0e h table 11, page 36 yes 04 h unused 05 h color tile configuration register 05 h table 12, page 37 no 06 h color tile row 1 definition register 44 h table 13, page 38 no 07 h color tile row 2 definition register ee h table 14, page 38 no 08 h color tile row 3 definition register 00 h table 15, page 39 no 09 h color tile row 4 definition register 00 h table 16, page 39 no 0a h negative voltage reference code register 76 h table 17, page 40 no 0b h positive voltage reference code register 80 h table 18, page 40 no 0c h power configuration register 00 h table 19, page 41 no 0d h factory use only fuo fuo fuo 0e h reset control register 00 h table 20, page 42 no 0f h device identification (read only) 50 h no table 7. i 2 c address assignments
revision 8.0 - 28 november 2001 : MCM20027 motorola 33 motorola semiconductor technical data imagemos imagemos 10 h exposure pga global gain register a 0e h table 23, page 44 yes 11 h unused 12h tristate control register ; table 21 03 h table 21, page 42 13h programable bias generator control register 00 h table 22, page 43 14-1f unused 20 h column dova dc register 00 h table 26, page 46 no 21 h exposure pga global gain register b 0e h table 24, page 45 yes 22 h pga gain mode 00 h table 25, page 45 no 23 h global dova register 00 h table 28, page 47 no 24 - 3f h unused 40 h capture mode control register 2a h table 29, page 48 yes 41 h sub-sample control register 10 h table 30, page 49 yes 42 h sync and strobe control register 02 h table 31, page 50 yes 43 h - 44 h unused 45 h woi row pointer msb register 00 h table 32, page 51 yes 46 h woi row pointer lsb register 10 h table 33, page 51 yes 47 h woi row depth msb register 03 h table 34, page 51 yes 48 h woi row depth lsb register ff h table 35, page 52 yes 49 h woi column pointer msb register 00 h table 36, page 52 yes 4a h woi column pointer lsb register 08 h table 37, page 53 yes 4b h woi column width msb register 04 h table 38, page 53 yes 4c h woi column width lsb register ff h table 39, page 53 yes 4d h factory use only 4e h integration time msb register 04 h table 40, page 54 yes 4f h integration time lsb register ff h table 41, page 55 yes 50 h virtual frame row depth msb register 04 h table 42, page 55 yes 51 h virtual frame row depth lsb register 27 h table 43, page 55 yes hex address register function defa ult ref. table shadow ed? table 7. i 2 c address assignments (continued)
motorola revision 8.0 - 28 november 2001 : MCM20027 34 motorola semiconductor technical data imagemos imagemos 52 h virtual frame column width msb register 05 h table 44, page 56 yes 53 h virtual frame column width lsb register 13 h table 45, page 56 yes 54 h sof delay register 4c h table 46, page 57 no 55 h vclk delay register 02 h table 47, page 57 no 56 h sof & vclk signal length control register 0e h table 47, page 57 no 57 h greycode and readout control register 04 h table 49, page 58 no 58 h - 5e h unused 5f h internal timing control register 1 (shs time definition) 0a h table 50, page 59 yes 60 h internal timing control register 2 (shr time definition) 0a h table 51, page 60 yes 61 h -63 h factory use only 64 h hclk delay register 5c h table 52, page 60 yes 65 h pixel data stream signal control register 00 h table 53, page 62 66 h factory use only 67 h frc definition register 24 h table 54, page 63 68 h factory use only 69 h - 7f h unused 80-bf mod64 column offset registers 00 h table 27, page 47 c0 h -ff h unused hex address register function defa ult ref. table shadow ed? table 7. i 2 c address assignments (continued)
revision 8.0 - 28 november 2001 : MCM20027 motorola 35 motorola semiconductor technical data imagemos imagemos 13.0 detailed register block assignments this section describes in further detail the functional op- eration of the various MCM20027 programmable regis- ters. the registers are subdivided into various blocks for ease of addressability and use (see table 6 ). in each table where a suffix code is used; h = hex, b = binary, and d = decimal. 13.1 analog register interface block the address range for this block is 00 h to bf h . 13.1.1 analog color configuration the four color gain registers, color tile configuration register , and four color tile row definitions define how white balance is achieved on the device. six-bit gain codes can be selected for four separate colors: table 8 , table 9 , table 10 , and table 11 . gain for each individ- ual color register is programmable given the gain func- tion defined in the table. the gain function used depends on what gain mode (white balance gain mode) the sensor is set ( pga gain mode ; table 25 ).the user programs these registers to account for changing light conditions to assure a white balanced output. the default value in each register is provides for a unity gain. in addition, the default cfa pattern color is listed in the title of each register. address 00 h dpga color 1 gain code green of green-red row default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg1[5] cg1[4] cg1[3] cg1[2] cg1[1] cg1[0] bit number function description reset state 7 - 6 unused unused xx 5 - 0 gain pga gain mode raw gain mode [cg1 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* cg1 d ) raw gain mode [cg1 d = 33-63 d ] --> gain = 1.391+ (0.0434* (cg1 d -32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 +(0.0434 x cg1 d ) (range 0.696 - 2.736) 001110 b table 8. dpga color 1 gain register address 01 h dpga color 2 gain code red default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg2[5] cg2[4] cg2[3] cg2[2] cg2[1] cg2[0] bit number function description reset state 7 - 6 unused unused xx table 9. dpga color 2 gain register
motorola revision 8.0 - 28 november 2001 : MCM20027 36 motorola semiconductor technical data imagemos imagemos 5 - 0 gain pga gain mode raw gain mode [cg2 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* cg2 d ) raw gain mode [cg2 d = 33-63 d ] --> gain = 1.391+ (0.0434* (cg2 d -32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 +(0.0434 x cg2 d ) (range 0.696 - 2.736) 001110 b address 01 h dpga color 2 gain code red default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg2[5] cg2[4] cg2[3] cg2[2] cg2[1] cg2[0] table 9. dpga color 2 gain register address 02 h dpga color 3 gain code blue default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg3[5] cg3[4] cg3[3] cg3[2] cg3[1] cg3[0] bit number function description reset state 7 - 6 unused unused xx 5 - 0 gain pga gain mode raw gain mode [cg3 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* cg3 d ) raw gain mode [cg3 d = 33-63 d ] --> gain = 1.391+ (0.0434* (cg3 d -32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 +(0.0434 x cg3 d ) (range 0.696 - 2.736) 001110 b table 10. dpga color 3 gain register address 03 h dpga color 4 gain code green of blue-green row default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg4[5] cg4[4] cg4[3] cg4[2] cg4[1] cg4[0] bit number function description reset state 7 - 6 unused unused xx table 11. dpga color 4 gain register
revision 8.0 - 28 november 2001 : MCM20027 motorola 37 motorola semiconductor technical data imagemos imagemos the color tile configuration register ; table 12 , defines the maximum number of lines and the maximum num- ber of colors per line. a maximum of four row and four column definitions are permitted. the color tile config- uration register defaults to two lines and two colors per line. the user should leave this register in default unless a unique cfa option has been ordered. this register can be configured to any pattern combina- tion of 1, 2, or 4 rows and 1, 2, or 4 columns. the color tile row definition registers; table 13 , table 14 , table 15 , and table 16 define the sequence of col- ors for each respective line. each byte wide line defini- tion allows a maximum of four unique color definitions using 2 bits per color in a given line. gain programming for each color was described earlier in this section. the default line definitions are colors 00 b , 01 b , 00 b , 01 b for row 1 and 10 b , 11 b , 10 b , 11 b for row 2 which supports a bayer pattern as defined in section 2.2 . the user should leave these registers in default unless a unique cfa op- tion has been ordered. for the default bayer configuration of the color filter ar- ray; figure 4 , the color gain register addresses are as follows: reg (01 h ): green pixel of a green-red row; reg (00 h ): red pixel; reg (03 h ): blue pixel; and reg (02 h ):green pixel of a blue-green row. the predefined 5 - 0 gain pga gain mode raw gain mode [cg4 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* cg4 d ) raw gain mode [cg4 d = 33-63 d ] --> gain = 1.391+ (0.0434* (cg4 d -32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 +(0.0434 x cg4 d ) (range 0.696 - 2.736) 001110 b address 03 h dpga color 4 gain code green of blue-green row default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x cg4[5] cg4[4] cg4[3] cg4[2] cg4[1] cg4[0] table 11. dpga color 4 gain register address 05 h color tile configuration default 05 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x nc[1] nc[0] nr[1] nr[0] bit number function description reset state 7 - 4 unused unused xxxx 3 - 2 columns 00 b = 1 column in tile. 01 b = 2 columns in tile. 1x b = 4 columns in tile. 01 b 1 - 0 rows 00 b = 1 row in tile. 01 b = 2 rows in tile. 1x b = 4 rows in tile. 01 b table 12. color tile configuration register
motorola revision 8.0 - 28 november 2001 : MCM20027 38 motorola semiconductor technical data imagemos imagemos gain values programmed in the respective registers are applied to pixel outputs as they are being read. address 06 h color tile row 1 definition green - red row default 44 h msb (7) 6 5 4 3 2 1 lsb (0) r1c4[1] r1c4[0] r1c3[1] r1c3[0] r1c2[1] r1c2[0] r1c1[1] r1c1[0] bit number function description reset state 7 - 6 color 4 fourth color in row 1(green) 01 b 5 - 4 color 3 third color in row 1 (red) 00 b 3 - 2 color 2 second color in row 1 (green) 01 b 1 - 0 color 1 first color in row 1 (red) 00 b table 13. color tile row 1 definition register address 07 h color tile row 2 definition blue - green row default ee h msb (7) 6 5 4 3 2 1 lsb (0) r2c4[1] r2c4[0] r2c3[1] r2c3[0] r2c2[1] r2c2[0] r2c1[1] r2c1[0] bit number function description reset state 7 - 6 color 4 fourth color in row 2 (blue) 11 b 5 - 4 color 3 third color in row 2 (green) 10 b 3 - 2 color 2 second color in row 2 (blue) 11 b 1 - 0 color 1 first color in row 2 (green) 10 b table 14. color tile row 2 definition register
revision 8.0 - 28 november 2001 : MCM20027 motorola 39 motorola semiconductor technical data imagemos imagemos 13.1.2 reference voltage adjust registers the analog register block allows programming the input voltage range of the analog to digital converter to match the saturation voltage of the pixel array. the voltage ref- erence generator can be programmed via two registers; nrv (0 to 1.25v) table 17 , prv (2.5v to 1.25v) table 18 , in 5mv steps. a 00 h value in the prv register represents a reference output voltage of 2.5v. a 00 h value in the nrv register represents output voltage of 0v. the de- fault settings for the two registers produce a 1.9v refer- ence on prv and 0.6v on nrv outputs. when adjusting address 08 h color tile row 3 definition unused default 00 h msb (7) 6 5 4 3 2 1 lsb (0) r3c4[1] r3c4[0] r3c3[1] r3c3[0] r3c2[1] r3c2[0] r3c1[1] r3c1[0] bit number function description reset state 7 - 6 color 4 fourth color in row 3 00 b 5 - 4 color 3 third color in row 3 00 b 3 - 2 color 2 second color in row 3 00 b 1 - 0 color 1 first color in row 3 00 b table 15. color tile row 3 definition register address 09 h color tile row 4 definition unused default 00 h msb (7) 6 5 4 3 2 1 lsb (0) r4c4[1] r4c4[0] r4c3[1] r4c3[0] r4c2[1] r4c2[0] r4c1[1] r4c1[0] bit number function description reset state 7 - 6 color 4 fourth color in row 4 00 b 5 - 4 color 3 third color in row 4 00 b 3 - 2 color 2 second color in row 4 00 b 1 - 0 color 1 first color in row 4 00 b table 16. color tile row 4 definition register
motorola revision 8.0 - 28 november 2001 : MCM20027 40 motorola semiconductor technical data imagemos imagemos these values, the user should keep the voltage range centered around 1.25v. 13.1.3 analog control registers the analog register block also contains a power con- figuration register ; table 19 , and a reset control reg- ister ; table 20 . the power configuration register controls the internal analog functionality that directly effect power consump- tion of the device. an external precision resistor pin is available on the MCM20027 that may be used to more accurately regulate the internal current sources. this serves to minimize variations in power consumption that are caused by variations in internal resistor values as well as offer a method to reduce the power consumption of the device. the default for this control uses the inter- nally provided resistor which is nominally 12.5k w . this feature is enabled by setting the res bit of the power configuration register and placing a resistor between the pin; extres, and ground. figure 11 depicts the power savings that can be achieved with an external re- sistor at a specific clock rate. power is further reduced at lower clock rates. the pbg bit of the power configuration register ; table 19 , is used to enable/disable the ?programmable bias generator?. when this bit is enabled, the user can vary the power consumption of the white balance pga (pgawb), exposure gain pga a (pgaexpa), expo- sure gain pga b (pgexpb), frame rate clamp (frc), column offset dova (col_dova), global offset dova (dove) and/or the analog to digital converter (a2d) between half an full current (power) consumption. in the programable bias generator control register ; ta- ble 22 . when this bit is disabled, it will use the power config- ured by the internal or external resistor (bit 3). address 0a h voltage reference ?negative? code default 76 h msb (7) 6 5 4 3 2 1 lsb (0) nrv[7] nrv[6] nrv[5] nrv[4] nrv[3] nrv[2] nrv[1] nrv[0] bit number function description reset state 7 - 0 reference voltage = 0.0 + (5mv * nrc d ) 01110110 b (0.6v) table 17. negative voltage reference code register address 0b h voltage reference ?positive? code default 80 h msb (7) 6 5 4 3 2 1 lsb (0) prv[7] prv[6] prv[5] prv[4] prv[3] prv[2] prv[1] prv[0] bit number function description reset state 7 - 0 reference voltage = 2.5 - (5mv * prv d ) 10000000 b (1.9v) table 18. positive voltage reference code register
revision 8.0 - 28 november 2001 : MCM20027 motorola 41 motorola semiconductor technical data imagemos imagemos the MCM20027 is put into a standby mode via the i 2 c interface by setting the sby bit of the power configura- tion register . additional control of the MCM20027 can be had using the reset control register; reset control register ; ta- ble 20 . setting the sir bit of this register will reset all the non programmable sensor interface registers to a known re- set state. setting the par bit of this register will reset all the sen- sors non programmable post adc registers to a known reset state. setting the asp bit of this register will reset all the sen- sors registers in the asp processing chain to a known reset state. setting the ssr bit of this register will reset all the non- user programmable registers to a known reset state. this is useful in situations when control of the MCM20027 has been lost due to system interrupts and the device needs only to be restarted using the earlier user programmed values. setting the sit bit allows the user to completely reset the MCM20027 to the default state via the serial control in- terface. for both reset bits, ssr and sit , the user must return those bits to 0 to enable continued operation address 0c h power configuration default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x pbg res ssc sc sby bit number function description reset state 7-5 unused unused x 4 prog bias gen 0 b = prog bias gen disabled 1 b = prog bias gen enabled 0 3 int/ext resistor 0 b = internal resistor 1 b = external resistor 0 b 2 select software clamp 0 b = select internal clamp 1 b = select software clamp 0 b 1 software clamp 0 b = clamp off 1 b = clamp on (if ssc = 1) 0 b 0 software standby 0 b = soft standby inactive 1 b = soft standby active 0 b table 19. power configuration register
motorola revision 8.0 - 28 november 2001 : MCM20027 42 motorola semiconductor technical data imagemos imagemos . the tristate control register ; table 21 is used to set signals into tristate mode. when the tsctl bit is reset (i.e.. ?0?) the hclk, sof, vclk, sync and strobe output signals are set to tristate mode. when the tspix bit is reset (i.e. ?0?) the pixel output data is set to tristate mode. address 0e h reset control default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x asr par sir ssr sit bit number function description reset state 7 - 5 unused unused xxx 4 asp (a2d) reset 0 b = normal mode 1 b = reset registers in the a2d to 0 0 b 3 post adc reset 0 b = normal mode 1 b = reset non-programmable post adc registers to reset state. 0 b 2 sensor interface reset 0 b = normal mode 1 b = reset non-programmable sensor interface resgisters to reset state. 0 b 1 state reset 0 b = normal mode 1 b = reset all non-programmable registers to the reset state 0 b 0 soft reset 0 b = normal mode 1 b = reset all registers. (same functions as setting the init pin) 0 b table 20. reset control register address 12 h tristate control b default 03 h msb (7) 6 5 4 3 2 1 lsb (0) fuo fuo fuo fuo fuo fuo tsctl tspix bit number function description reset state 7 - 3 fuo factory use only 000000 b 1 tsctl 0 - outputs in tristate 1 - outputs driving 1 b table 21. tristate control register
revision 8.0 - 28 november 2001 : MCM20027 motorola 43 motorola semiconductor technical data imagemos imagemos the programable bias generator control register ; ta- ble 22 can be used by the user to vary the power con- sumption of the white balance pga (pgawb), exposure gain pga a (pgaexpa), exposure gain pga b (pgexpb), frame rate clamp (frc), column offset dova (col_dova), global offset dova (dove) and/ or the analog to digital converter (a2d) between half an full current (power) consumption. in order for this register to be used, the pbg bit of the power configuration register ; table 19 has to be en- abled. 0 tspix 0 - outputs in tristate 1 - outputs driving 1 b address 12 h tristate control b default 03 h msb (7) 6 5 4 3 2 1 lsb (0) fuo fuo fuo fuo fuo fuo tsctl tspix table 21. tristate control register address 13 h programable bias generator control default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x adp gdp egb ega wbp cdp fcp bit number function description reset state 7 unused unused x b 6 a to d converter (a2d) 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b 5 global dova 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b 4 pga exp. gain b 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b 3 pga exp. gain a 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b 2 pga white balance 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b 1 col_dova 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b table 22. programable bias generator control register
motorola revision 8.0 - 28 november 2001 : MCM20027 44 motorola semiconductor technical data imagemos imagemos 13.2 gain calibration block the exposure pga global gain register a ; table 23 and the exposure pga global gain register b ; table 24 , allows the user to set a global gain via two 6 bit reg- ister which are applied universally to all the pixel out- puts. this enables the user to account for varying light conditions.the gain range depends on what the expo- sure gain mode ( pga gain mode ; table 25 )is set. if the exposure gain mode is set at either raw or linear, then exposure pga global gain register a ; table 23 and exposure pga global gain register b ; table 24 are both utilized. but if it is set at linear 2 gain mode, then only exposure pga global gain register a ; table 23 is used. ( 0 frame rate clamp 1 b = full current (power) consumption [80/100] 0 b = half current (power) consumption [40/50] 0 b address 13 h programable bias generator control default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x adp gdp egb ega wbp cdp fcp table 22. programable bias generator control register address 10 h exposure pga global gain a default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x gg1[5] gg1[4] gg1[3] gg1[2] gg1[1] gg1[0] bit number function description reset state 7 - 6 unused unused xx 5 - 0 gain pga gain mode raw gain mode [gg1 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* gg1 d ) raw gain mode [gg1 d = 33-63 d ] --> gain = 1.391+ (0.0434* (gg1 d - 32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 + (0.0434 * gg1 d ) (range 0.696 - 2.736) linear 2 gain mode ----> gain = 0.484 +(0.12 x gg1 d ) (range 0.484 - 7.488) 001110 table 23. exposure pga global gain register a
revision 8.0 - 28 november 2001 : MCM20027 motorola 45 motorola semiconductor technical data imagemos imagemos the pga gain mode ; table 25 , is the register where the pga gain modes for the white balance and exposure gains can be selected. there are two different gain modes for white balance and there are three different gain modes for the exposure gain. white balance gain modes: 1) raw gain mode - 32 steps @ 0.02174/step - 32 steps @ 0.04340/step 2) linear gain mode - 48 steps @ 0.04340/step exposure gain modes: 1) raw gain mode - 32 steps @ 0.02174/step - 32 steps @ 0.04340/step i.e. pga global gain a register= raw gain mode pga global gain b register= raw gain mode 2) linear gain mode - 48 steps @ 0.04340/step i.e. pga global gain a register= linear gain mode pgaglobal gain b register= linear gain mode 3) linear 2 gain mode - 64 steps @ ~ 0.12/step i.e. pga global gain a register= linear 2 gain mode pga global gain b register= not used the wbm bit sets the white balance mode. while the egm [d] bit sets the exposure gain mode address 21 h exposure pga global gain b default 0e h msb (7) 6 5 4 3 2 1 lsb (0) x x gg2[5] gg2[4] gg2[3] gg2[2] gg2[1] gg2[0] bit number function description reset state 7 - 6 unused unused xx b 5 - 0 gain pga gain mode raw gain mode [gg2 d = 0-32 d ] ---> gain = 0.6956 + (0.02174* gg2 d ) raw gain mode [gg2 d = 33-63 d ] --> gain = 1.391+ (0.0434* (gg2 d - 32) (range 0.696 - 2.736) linear gain mode -----> gain = 0.6956 + (0.0434 * gg2 d ) (range 0.696 - 2.736) 001110 table 24. exposure pga global gain register b address 22 h pga gain mode default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wbm egm[1] egm[0] bit number function description reset state table 25. pga gain mode
motorola revision 8.0 - 28 november 2001 : MCM20027 46 motorola semiconductor technical data imagemos imagemos 13.3 offset calibration block offset adjustments for the MCM20027 are done in sep- arate sections of the asp to facilitate fpn removal and final image black level set. the column dova dc register ; table 26 , is used to set the initial offset of the pixel output in a range that will facilitate per-column offset data generation for varying operational conditions. in most operational scenarios, this register can be left in its default state of 00 h . this is a pre-image processing gain in comparison to the glo- bal dova register which is a post image processing chain gain (pre a2d gain). this register can also be used to apply a global offset adjust. in this case, the user must take into account the color gain and global gain registers to determine the resulting offset at the output. the mod64 column offset registers ; table 27 are used in conjunction with the column dova dc register ; ta- ble 26 to reduce/eliminate fixed pattern noise (fpn). there are 64 registers that can be programmed with in- dividual offset values. they will be applied to all the col- umns on a single image frame on a modular 64 basis.i.e. register 80 h column offset will be applied to column 0 , register 81 h column offset will be applied to column 1, register bf h column offset will be applied to column 63, register 80 h column offset will be applied to column 0..etc.. 7 - 3 unused unused xxxx 2 white bal- ance gain mode 0 b = raw gain mode 1 b = linear gain mode 0 b 1 - 0 exposure gain mode 00 b = raw gain mode 01 b = linear gain mode 1x b = linear 2 gain mode 00b address 22 h pga gain mode default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wbm egm[1] egm[0] table 25. pga gain mode address 20 h column dova dc default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x cdd[5] cdd[4] cdd[3] cdd[2] cdd[1] cdd[0] bit number function description reset state 7 - 6 unused unused xx 5 sign 0 b = positive offset 1 b = negative offset 0 b 4 - 0 column dc offset offset = 2.6 * cdd d (64 steps @ 2.6mv /step) 00000 b table 26. column dova dc register
revision 8.0 - 28 november 2001 : MCM20027 motorola 47 motorola semiconductor technical data imagemos imagemos the global dova register ; table 28 performs a final offset adjustment in analog space prior to the adc. the 6-bit register uses its msb to indicate positive or nega- tive offset. each bit value changes the offset value by 4 lsb code levels hence giving an offset range of +/-124 lsb. as an example, to program an offset of +92 lsb, the binary representation of +23 d i.e. 010111 b should be loaded. 13.4 sensor interface block 13.4.1 sensor output control the sensor output control registers define how the win- dow of interest is captured and what data is output from the MCM20027. the capture mode control register ; table 29 , defines how the data is captured and how the data is to be pro- vided at the output.. setting the cms bit will stop the current output data stream at the end of the current frame. unsetting this bit ( cms = 0 b ) will resume the output of the frame stream. the MCM20027 is in cfrs in default. the user may use this bit to capture data in the cfrs mode and/or sfrs while using the sync pin. the sync pin triggers a single frame of data to be output from the device in the address 80-bf h mod64 column offset default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x mdd[5] mdd[4] mdd[3] mdd[2] mdd[1] mdd[0] bit number function description reset state 7 - 6 unused unused xx 5 sign 0 b = positive offset 1 b = negative offset 0 b 4 - 0 mod 64 column dc offset offset = 2.6 * mdd d (64 steps @ 2.6mv /step) 00000 b table 27. mod64 column offset registers address 23 h global dova default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x gd[5] gd[4] gd[3] gd[2] gd[1] gd[0] bit number function description reset state 7 - 6 unused unused xx 5 sign 0 b = positive offset 1 b = negative offset 0 b 4 - 0 offset offset = 12 * gd d (64 steps @ 12mv /step) 00000 b table 28. global dova register
motorola revision 8.0 - 28 november 2001 : MCM20027 48 motorola semiconductor technical data imagemos imagemos sfrs mode. please refer to figure 14, on page20 for a timing diagram of this mode. the sp bit is used to define whether sof is active high or low. sof is active high in default. the ve bit is used to determine whether vclk is output at the beginning of all the rows including virtual frame rows or for the woi rows only. the default is woi only. the vp bit is used to define whether vclk is active high or low. vclk is active high in default. the he bit is used to determine whether hclk is output continuously or for the woi pixels only. the default is woi only. the hp bit is used to define whether hclk is active high or low. hclk is active high in default. the hm bit is used to define hclk is toggled or wheth- erwhether it is continuously output. the sub-sample control register ; table 30 , is used to define what pixels of the woi are read and the method they are read. using the cm bit, the user can sample the pixel array in either monochrome or bayer pattern color space. this means that when sampling the rows or columns, the set of pixels read will be gathered as individual pixels (monochrome) or in color tiles of pixels (bayer pattern). the pixels will be read in monochrome mode in default. the row sub sampling rate is defined by rf [1:0] while the column sub sampling rate is defined by cf [1:0]. the pix- el array is fully sampled in default. address 40 h capture mode control default 2a h msb (7) 6 5 4 3 2 1 lsb (0) fuo cms sp ve vp he hp hm bit number function description reset state 7 fuo factory use only 0 b 6 capture mode 0 b = continuos frame rolling shutter 1 b = single frame rolling shutter 0 b 5 sof phase 1 b = sof active high 0 b = sof active low 1 b 4 vclk enable 1 b = all virtual frame rows 0 b = window of interest rows only 0 b 3 vclk phase 1 b = active high 0 b = active low 1 b 2 hclk enable 1 b = continuous 0 b = window of interest pixels only 0 b 1 hclk phase 1 b = active high 0 b = active low 1 b 0 hclk mode 1 b = continuous - envelope 0 b = toggles - like mclk 0 b table 29. capture mode control register
revision 8.0 - 28 november 2001 : MCM20027 motorola 49 motorola semiconductor technical data imagemos imagemos the sync and strobe control register ; table 31 is used to control the sync and strobe signals. the sr bit when enabled causes the sync signal to go high for exactly one clock cycle, and then returns to a low. it remains low until the sr bit is enabled again. the sa bit when enabled causes the sync signal high until this bit is disabled. this causes continuous frame processing. the se bit when enabled will allow for an external signal to drive the sync signal via the sync pin on the chip. the sae bit when enabled will enable the strobe sig- nal to be generated automatically by the sensor.this will only work in sfrs (single frame rolling shutter). the strobe signal is goes high when all the rows in the frame are integrating together. the saw bit allows the user to select how long the strobe signal is going to be on. if the bit is set to 1 (setting 1), causes the strobe signal to be on from the time all the rows are integrating to 1 row time (t row ) before read-out of the first row commences. if the bit is set to 0 (setting 0), causes the strobe signal to on for a duration of 1 row time (t row ) from the time all rows are integrating the sso bit ,when enabled, forces the strobe signal and thereby the strobe pin high until it is reset back to 0. when this bit is set high - the sae and saw bit set- tings become negligible. note! please refer to figure 15, on page14 for strobe signal timing diagram. address 41 h sub-sample control default 10 h msb (7) 6 5 4 3 2 1 lsb (0) x fuo fuo cm rf[1] rf[0] cf[1] cf[0] bit number function description reset state 7 unused unused x 6-5 fuo factory use only fuo 4 color mode 1 b = bayer pattern sampling 0 b = monochrome pattern sampling 1 b 3 - 2 row fre- quency 11 b = read one row pattern, skip 7 (1/8 sampled) 10 b = read one row pattern, skip 3 (1/4 sampled) 01 b = read one row pattern, skip one (1/2 sampled) 00 b = full sampling 00 b 1 - 0 column frequency 11 b = read one column pattern, skip 7 (1/8 sampled) 10 b = read one column pattern, skip 3 (1/4 sampled) 01 b = read one column pattern, skip one (1/2 sampled) 00 b = full sampling 00 b table 30. sub-sample control register
motorola revision 8.0 - 28 november 2001 : MCM20027 50 motorola semiconductor technical data imagemos imagemos 13.4.2 programmable ?window of interest? the woi is defined by a set of registers that indicate the upper-left starting point for the window and another set of registers that define the size of the window. please refer to figure 9, on page12 for a pictorial representa- tion of the woi within the active pixel array. the woi row pointer; wrp [10:0] ( table 32 and table 33 ), and the woi column pointer; wcp [10:0] ( table 36 and table 37 ), mark the upper-left starting point for the woi. the woi row pointer; wrp [10:0], has a range of 0 d to 1047 d whereas the woi column pointer; wcp [10:0] has a usable range of 0 d to 1295 d . the pointer can be placed anywhere within the active pixel array. the woi row depth; wrd [10:0] ( table 32 and table 33 ), and the woi column depth; wcd [10:0] ( table 36 and table 37 ), indicate the size of the woi. the woi row depth; wrd [10:0], has a range of 0 d to 1047 d whereas the woi column depth; wcd [10:0], has a range of 0 d to 1295 d . the user should be careful to create a woi that con- tains active pixels only. there is no logic in the sensor address 42 h sync and strobe control default 02 h msb (7) 6 5 4 3 2 1 lsb (0) x x sso saw sae se sa sr bit number function description reset state 7-6 unused unused xx 5 strobe enable 1 b = strobe on 0 b = disabled 0 b 4 strobe auto width definition 1 b = maximum time (entire time during which all active rows are inte grating) 0 b = 1 line 0 b 3 strobe auto enabled 1 b = enabled during integration 0 b = disabled 0 b 2 exernal sync enabled 1 b = enabled 0 b = disabled 0 b 1 sync always 1 b = enabled 0 b = disabled 1 b 0 sync request 1 b = enabled (self clearing - will always read ?0?) 0 b = disabled 0 b table 31. sync and strobe control register
revision 8.0 - 28 november 2001 : MCM20027 motorola 51 motorola semiconductor technical data imagemos imagemos interface to prevent the user from defining an woi that addresses non-existent pixels. address 45 h woi row pointer msb default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wrp[10] wrp[9] wrp[8] bit number function description reset state 7 - 3 unused unused xxxxx 2 - 0 woi row pointer in conjunction with the woi row pointer lsb register ( table 33 ), forms the 11-bit woi row pointer wrp[10:0] 000 b table 32. woi row pointer msb register address 46 h woi row pointer lsb default 10 h msb (7) 6 5 4 3 2 1 lsb (0) wrp[7] wrp[6] wrp[5] wrp[4] wrp[3] wrp[2] wrp[1] wrp[0] bit number function description reset state 7 - 0 woi row pointer in conjunction with the woi row pointer msb register ( table 32 ), forms the 11-bit woi row pointer wrp[10:0] 00010000 b (row 16) table 33. woi row pointer lsb register address 47 h woi row depth msb default 03 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wrd[10] wrd[9] wrd[8] bit number function description reset state 7 - 3 unused unused xxxxx table 34. woi row depth msb register
motorola revision 8.0 - 28 november 2001 : MCM20027 52 motorola semiconductor technical data imagemos imagemos 2-0 woi row depth in conjunction with the woi row depth lsb register ( table 35 ), forms the 11-bit woi row depth wrd[10:0]. 011 b address 47 h woi row depth msb default 03 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wrd[10] wrd[9] wrd[8] table 34. woi row depth msb register address 48 h woi row depth lsb default ff h msb (7) 6 5 4 3 2 1 lsb (0) wrd[7] wrd[6] wrd[5] wrd[4] wrd[3] wrd[2] wrd[1] wrd[0] bit number function description reset state 7 - 0 woi row pointer in conjunction with the woi row depth msb register ( table 34 ), forms the 11-bit woi row depth wrd[10:0]. desired = wrd d + 1. 11111111 b (1024 rows) table 35. woi row depth lsb register address 49 h woi column pointer msb default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wcp[10] wcp[9] wcp[8] bit number function description reset state 7 - 3 unused unused xxxxx 2 - 0 woi col. pointer in conjunction with the woi column pointer lsb register ( table 37 ), forms the 11-bit woi column pointer wcp[10:0] 000 b table 36. woi column pointer msb register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 53 imagemos imagemos address 4a h woi column pointer lsb default 08 h msb (7) 6 5 4 3 2 1 lsb (0) wcp[7] wcp[6] wcp5] wcp[4] wcp[3] wcp[2] wcp[1] wcp[0] bit number function description reset state 7 - 0 woi col. pointer in conjunction with the woi column pointer msb register ( table 36 ), forms the 11-bit woi column pointer wcp[10:0] 00001000 b (col. 8) table 37. woi column pointer lsb register address 4b h woi column width msb default 04 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x x wcw[10] wcw[9] wcw[8] bit number function description reset state 7 - 3 unused unused xxxxx 2 - 0 woi col. width in conjunction with the woi column width lsb register ( table 39 ), forms the 11-bit woi column width wcw[10:0]. 100 b table 38. woi column width msb register address 4c h woi column width lsb default ff h msb (7) 6 5 4 3 2 1 lsb (0) wcw[7] wcw[6] wcw[5] wcw[4] wcw[3] wcw[2] wcw[1] wcw[0] bit number function description reset state 7 - 0 woi row pointer in conjunction with the woi column width msb register ( table 38 ), forms the 11-bit woi column width wcw[10:0]. desired = wcw d + 1. 11111111 b (1280 col.) table 39. woi column width lsb register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 54 imagemos imagemos 13.4.3 integration time control the integration time registers; table 41 , table 40 , and table 41 , control the integration time for the pixel array. integration time for cfrs and sfrs; cint [13:0], is measured in virtual row times. please refer to figure 11 for a pictorial description of the virtual frame and its relationship to the woi. note!! the upd bit of the integration time msb reg- ister ; table 40 is used to indicate a change to cint [13:0]. since multiple i2c writes may be needed to complete desired frame to frame integration time changes, the upd bit signals that all desired programming has been completed, and to apply these changes to the next frame captured. this prevents undesirable changes in integration time that may result from i2c writes that span the ?end of frame? boundary. this upd bit has to be toggled from its previous state in order for the new value of cint [13:0] to be accepted/updated by the sen- sor and take effect. i.e. if its previous state is ?0?, when writing a new cint value, first write cint[7:0] to the inte- gration time lsb register ; table 41 , then write both cint [13:8] and ?1? to the upd bit to the integration time msb register ; table 40 . a virtual frame is the mechanism by which the user con- trols the integration time and frame time for the output data stream. by adding additional rows or columns as ?blanking? to the woi to form the virtual frame, the user can control the amount of blanking in both horizontal and vertical space.( table42, ? virtual frame row depth msb register ,? on page55 table43, ? virtual frame row depth lsb register ,? on page55 table44, ? virtual frame column width msb register ,? on page56 table45, ? virtual frame column width lsb register ,? on page56 ) the user should be careful to create a virtual frame that is larger than the woi. there is no logic in the sen- sor interface to prevent the user from defining a virtual frame smaller than the woi. therefore, pixel data may be lost. the virtual frame must be at least 1 row and 6 columns larger than the woi. the virtual frame completely defines the integration time in cfrs. any changes to the woi or how the woi is sampled has no effect on integration time. address 4e h integration time msb default 04 h msb (7) 6 5 4 3 2 1 lsb (0) fuo upd cint[13] cint[12] cint[11] cint[10] cint[9] cint[8] bit number function description reset state 7 fuo factory use only 6 integration time update switch this bit has to change from its previous state everytime a new value is written to integration time isb and the integration time lsb . 0 5 - 0 integration time in conjunction with the integration time lsb ( table 41 ) register, forms the 14-bit integration time cint[13:0]. 000100 b table 40. integration time msb register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 55 imagemos imagemos address 4f h integration time lsb default ff h msb (7) 6 5 4 3 2 1 lsb (0) cint[7] cint[6] cint[5] cint[4] cint[3] cint[2] cint[1] cint[0] bit number function description reset state 7 - 0 integration time in conjunction with the integration time isb ( table 40 ) register, forms the 14-bit integration time cint[13:0]. integration time = (cint d + 1) * t row 11111111 b cfrs and sfrs : 1280 rows) table 41. integration time lsb register address 50 h virtual frame row depth msb default 04 h msb (7) 6 5 4 3 2 1 lsb (0) x x vrd[13] vrd[12] vrd[11] vrd[10] vrd[9] vrd[8] bit number function description reset state 7 - 6 unused unused xx 5 - 0 virtual row depth in conjunction with the cfrs and sfrs virtual frame row depth lsb ( table 43 ) register, forms the 14-bit virtual frame row depth vrd[13:0]. 000100 b table 42. virtual frame row depth msb register address 51 h virtual frame row depth lsb default 27 h msb (7) 6 5 4 3 2 1 lsb (0) vrd[7] vrd[6] vrd[5] vrd[4] vrd[3] vrd[2] vrd[1] vrd[0] bit number function description reset state table 43. virtual frame row depth lsb register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 56 imagemos imagemos 7 - 0 virtual row depth in conjunction with the cfrs and sfrs virtual frame row depth msb ( table 42 ) register, forms the 14-bit virtual frame row depth vrd[13:0]. woi is always top-left justified in virtual frame. vrd d minimum = wrd d + 1 00100111 b (1064 rows) address 51 h virtual frame row depth lsb default 27 h msb (7) 6 5 4 3 2 1 lsb (0) vrd[7] vrd[6] vrd[5] vrd[4] vrd[3] vrd[2] vrd[1] vrd[0] table 43. virtual frame row depth lsb register address 52 h virtual frame column width msb default 05 h msb (7) 6 5 4 3 2 1 lsb (0) x x vcw[13] vcw[12] vcw[11] vcw[10] vcw[9] vcw[8] bit number function description reset state 7 - 6 unused unused xx 5 - 0 virtual col- umn width in conjunction with the cfrs and sfrs virtual frame column width lsb ( table 45 ) register, forms the 14-bit virtual frame col- umn width vcw[13:0]. 000101 b table 44. virtual frame column width msb register address 53 h virtual frame column width lsb default 13 h msb (7) 6 5 4 3 2 1 lsb (0) vcw[7] vcw[6] vcw[5] vcw[4] vcw[3] vcw[2] vcw[1] vcw[0] bit number function description reset state 7 - 0 virtual col- umn width in conjunction with the cfrs and sfrs virtual frame column width msb ( table 44 ) register, forms the 14-bit virtual frame col- umn width vcw[13:0]. woi is always top-left justified in virtual frame. vcw d minimum = wcw d + 11 00010011 b (1300 col.) table 45. virtual frame column width lsb register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 57 imagemos imagemos the sof delay register ; table 46 and vclk delay register ; table 47 are used to determine the time (clock) delay for the start of the two signals respectively. the sof delay is measured as the time after the start of the change of row address (change of row address is a parameter that cannot be easily identified by the common user). the vclk delay is defined as the time after the sof signal is first initialized. the sof & vclk signal length control register , table 48 , is used to de- fine the size of the sof and vclk signals. in default, sof is one row wide while vlck is 64 mclks wide address 54 h sof delay default 4c h msb (7) 6 5 4 3 2 1 lsb (0) sofd[7] sofd[6] sof[d5] sofd[4] sofd[3] sofd[2] sofd[1] sofd[0] bit number function description reset state 7 - 0 sof delay delay= sofd[d] x 0.5 mclks (note - delay is relative to internal pixel transfer control) 1001100b table 46. sof delay register address 55 h vclk delay default 02 h msb (7) 6 5 4 3 2 1 lsb (0) vckd[7] vckd[6] vckd[5] vckd[4] vckd[3] vckd[2] vckd[1] vckd[0] bit number function description reset state 7 - 0 vclk delay delay = vckd[d] x 0.5 mclks (note - delay is relative to start of frame {sof} signal) 00000010 b table 47. vclk delay register address 56 h sof and vclk signal length control default e h msb (7) 6 5 4 3 2 1 lsb (0) x x x x sofc[3] sofc[2] vckc[1] vckc[0] bit number function description reset state 3 - 2 sof con- trol sof[3:2] = 00 b = 1 mclk wide sof[3:2] = 01 b = 8 mclks wide sof[3:2] = 10 b = 64 mclks wide sof[3:2] = 11 b = full row wide 11 b table 48. sof & vclk signal length control register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 58 imagemos imagemos the greycode and readout control register ; table 49 allows the user to choose if the column and row addresses are to utilize greycode address format or not. it also allows the user to select the user to select the direction of the row and column readout. the rrc when enabled causes the column data to be readout in the reverse direction as compared to the normal readout direction. the rrr when enabled causes the row data to be readout in the reverse direction as compared to the normal readout direction. the gcc bit when enabled causes the column addresses to be greycoded. the gcr bit when enabled causes the column addresses to be greycoded. 1 - 0 vclk con- trol vck[1:0] = 00 b = 1 mclk wide vck[1:0] = 01 b = 8 mclks wide vck[1:0] = 10 b = 64 mclks wide vck[1:0] = 11 b = full row wide 10 b address 57 h greycode and readout control default 04 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x gcr gcc rrr rrc bit number function description reset state 7-4 unused unused 3 row grey- code address 1 b = greycode addressing enabled 0 b = binary addressing 0 b 2 column greycode address enable 1 b = greycode addressing enabled 0 b = binary addressing 1 b table 49. greycode and readout control register address 56 h sof and vclk signal length control default e h msb (7) 6 5 4 3 2 1 lsb (0) x x x x sofc[3] sofc[2] vckc[1] vckc[0] table 48. sof & vclk signal length control register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 59 imagemos imagemos the internal timing control register 1 (shs time definition) ; table 50 and , internal timing control register 2 (shr time definition) ; table 51 are used to define the size of internal timing pulse widths. in default, both shs and shr are 6 mclk?s wide. a maximum of 64 mclk?s can be programmed for the shs delay and another 64 mclk?s for the shr delay, for a total 0f 128 mclk?s. note! writing 00h to either of these registers will write a maximum timing delay of 64 mclk?s. i.e. 00 = 64 mclk 1 row read- out 1 b = reverse readout (top to bottom) 0 b = normal readout (bottom to top) 0 b 0 column readout 1 b = reverse readout (right to left) 0 b = normal readout (left to right 0 b address 5f h internal timing control default 0a h msb (7) 6 5 4 3 2 1 lsb (0) x x shs[5] shs[4] shs[3] shs[2] shs[1] shs[0] bit number function description reset state 7-6 unused unused xx 5 - 0 shs shs[5:0] = 000000 b = 64 mclks wide shs[5:0] = 000001 b = 1 d mclks wide shs[5:0] = 000010 b = 2 d mclks wide shs[5:0] = 000011 b = 3 d mclks wide | | shs[5:0] = 111111 b = 63 d mclks wide 001010b table 50. internal timing control register 1 (shs time definition) address 57 h greycode and readout control default 04 h msb (7) 6 5 4 3 2 1 lsb (0) x x x x gcr gcc rrr rrc table 49. greycode and readout control register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 60 imagemos imagemos the hclk delay register ; table 52 allows the user to program the delay for the start of the hclk signal. the delay is calculated in accordance to the result of inserting the value of the register into the following formula: delay = ((hckd[d]-4)x 0.5) - 16 mclks address 60 h internal timing control default 0a h msb (7) 6 5 4 3 2 1 lsb (0) x x shr[5] shr[4] shr[3] shr[2] shr[1] shr[0] bit number function description reset state 7-6 unused unused xx 5 - 0 shr shr[5:0] = 000000 b = 64 mclks wide shr[5:0] = 000001 b = 1 d mclks wide shr[5:0] = 000010 b = 2 d mclks wide shr[5:0] = 000011 b = 3 d mclks wide | | shr[5:0] = 111111 b = 63 d mclks wide 001010b table 51. internal timing control register 2 (shr time definition) address 64 h hclk control default 5c h msb (7) 6 5 4 3 2 1 lsb (0) x fuo fuo fuo fuo hckd[2] hckd[1] hckd[0] bit number function description reset state 7 unused unused x 6 - 3 fuo factory use only table 52. hclk delay register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 61 imagemos imagemos the pixel data stream control register allows the user to select how the output pixel data stream is encoded/for- matted. the vcb bit allows the user to force all the blanking data coming out of the a2d to be 0. the vcg bit allows the user to choose between encoded pixel data output stream or non-encoded pixel data output stream. the vcc bit allows the user to clip the output active pixel data to lie between 001 and 3fe the default mode ( normal mode) has the sof, hclk, vclk etc. signals being utilised to indicate the start of data and the end of data. ( figure 2, on page7 and figure 14, on page20 ) register value = 00 h another mode, video mode is a mode where the sof and row start/end signals are encoded (contained) in the active pixel data stream. in addition, all data that is not a sof, row start/end, or active pixel data are forced to 0. i.e. all blanking data from the a2d are forced to 0. the following sequence identifies the signals below: (see figure , on page30 ) a) sof (1st row of pixel data) - ?3ff x 4) b) start of all other rows - ?3ff x 2? then ?000 x 2? 2 - 0 hclk delay delay = ((hckd[d]-4)x 0.5) - 16 mclks 100 b address 64 h hclk control default 5c h msb (7) 6 5 4 3 2 1 lsb (0) x fuo fuo fuo fuo hckd[2] hckd[1] hckd[0] table 52. hclk delay register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 62 imagemos imagemos register value = 70 the frc definition register ; table 54 allows the user to define the size of the dark rows to use as clamping rows. the frcs bit identifies the starting position of the clamping rows. i.e. if 4d is written to this register, the first clamped dark row would be the 4th row. the frcd bit identifies the frc row depth. allows the user to select the number of dark rows to clamp on. note! since there exists only 11 dark rows the addition of frc row depth + frc row start should not be great- er than 11, otherwise light rows would be clamped in the process. address 65 h pixel data stream signal control register default 00 h msb (7) 6 5 4 3 2 1 lsb (0) x vcb vsg vcc fuo fuo fuo fuo bit number function description reset state 7 unused unused x 6 vcode blanking 1 b = all blanking data will be forced to 0 0 b = blanking of data 0 b 5 vcode sync gen- eration 1 b = prefixes 3ff x 4 to beginning of active pixel data to indicate start of row 1(sof signal). prefixes 3ff x 2 and then 000 x 2 to indicate start of all following rows of data (vclk) [encoded data stream] 0 b = use of sof, hclk etc. signals for sync generation (no coded data stream) 0 b 4 vcode clipping 1 b = will clip output data stream to values 001 b to 3fe b 0 b = no clipping of output data stream 0 b 3 - 0 fuo factory use only 0000 b table 53. pixel data stream signal control register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 63 imagemos imagemos address 67 h frc definition default 24 h msb (7) 6 5 4 3 2 1 lsb (0) x fuo frcd[1] frcd[0] frcs[3] frcs[2] frcs[1] frcs[0] bit number function description reset state 7 unused unused x 6 fuo factory use only 5 - 4 frc row depth defines the number of clamping rows. note!! the addition of frc row depth + frc row start should not be greater than 11 d . 10 b 3 - 0 frc row start defines the first clamping row. defines the frc starting point. 0100 table 54. frc definition register
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 64 imagemos imagemos 14.0 electrical characteristics absolute maximum ratings 1 (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage -0.5 to 3.8 v v in dc input voltage 0.5 to v dd + 0.5 v v out dc output voltage -0.5 to v dd + 0.5 v i dc current drain per pin, any single input or output 50 ma i dc current drain, v dd and v ss pins 100 ma t stg storage temperature range -65 to +150 c t l lead temperature (10 second soldering) 300 c 1 maximum ratings are those values beyond which damage to the device may occur. v ss = av ss = dv ss = v sso (dv ss = v ss of digital circuit, av ss = v ss of analog circuit) v dd = av dd = dv dd = v ddo (dv dd = v dd of digital circuit, av dd = v dd of analog circuit) recommended operating conditions (to guarantee functionality; voltage referenced to v ss ) symbol parameter min. max unit v dd dc supply voltage, v dd = 3.3v (nominal) 3.0 3.6 v t a commercial operating temperature 0 40 c t j junction temperature 0 55 c notes: - all parameters are characterized for dc conditions after thermal equilibrium has been established. - unused inputs must always be tied to an appropriate logic level, e.g., either v ss or v dd . - this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, i t is advised that normal precautions be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedanc e circuit. - for proper operation it is recommended that v in and v out be constrained to the range v ss < (v in or v out ) < v dd . dc electrical characteristics (v dd = 3.3v 0.3v ; v dd referenced to v ss ; t a = 0c to 40c) t a = 0 c to 40 c symbol characteristic condition min. max unit v ih input high voltage 2.0 v dd +0.3 v v il input low voltage -0.3 0.8 v i in input leakage current, no pull-up resistor v in = v dd or v ss -5 5 m a
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 65 imagemos imagemos i oh output high current v dd = min., v oh min. = 0.8 * v dd -3 ma i ol output low current v dd = min., v ol max = 0. 4 v 3 ma v oh output high voltage v dd = min., i oh = -100 m a v dd - 0.2 v v ol output low voltage v dd = min., i ol = 100 m a 0.2 v i oz 3-state output leakage current output = high impedance, v out = v dd or v ss -10 10 m a i dd maximum standby supply current i out = 0ma , v in = v dd or v ss 0 15.0 m a power dissipation (vdd = 3.0v, vdd referenced to vss; at = 25 c ) symbol parameter condition typ unit p stdby standby power init pin logic high 100 uw p avg average power 13.5 mhz operation 250 mw MCM20027 monochrome cmos image sensor electro-optical characteristics symbol parameter typ unit notes e sat saturation exposure 0.14 m j/cm 2 1 qe peak quantum efficiency (@550nm) 18 % 2 prnu photoresponse non-uniformity 12 % pk-pk 3 notes: 1. for l = 550 nm wavelength. 2. refer to typical values from figure 3 , MCM20027 nominal spectral response. 3. for a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. MCM20027 color cmos image sensor electro-optical characteristics symbol parameter typ unit notes e sat saturation exposure 0.3 m j/cm 2 1 qe r red peak quantum efficiency @ l = 650 nm 12 % 2 qe g green peak quantum efficiency @ l = 550 nm 11 % 2 qe b blue peak quantum efficiency @ l = 450 nm 8 % 2 notes: 1. for l = 550 nm wavelength. 2. refer to typical values from figure 3 , MCM20027 nominal spectral response. cmos image sensor characteristics symbol parameter typ unit notes sensitivity 1.8 v/lux-sec i d photodiode dark current 0.2 na/cm 2 dsnu dark signal non-uniformity (entire field) 0.4 % rms cte pixel charge transfer efficiency 0.9995 % 1 f h horizontal imager frequency 11.5 mhz 4 x ab blooming margin - shuttered light 200 2,3
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 66 imagemos imagemos analog signal processor characteristics notes: 1. transfer efficiency of photosite 2. x ab represents the increase above the saturation-irradiance level (h sat ) that the device can be exposed to before blooming of the pixel will occur. 3. no column streaking 4. at 30fps vga general symbol parameter typ unit notes n e - total total system (equivalent) noise floor 70 e - rms 1 dr system dynamic range 50 db notes: 1. includes amplifier noise, dark pattern noise and dark current shot noise at 13.5 mhz data rates. analog to digital converter (adc) symbol parameter min typ max units resolution 10 bits v in input dynamic range 8 2.5 vpp inl integral non-linearity + 1.0 lsb dnl differential non-linearity + 0.5 lsb f max adc clock rate 13.5 mhz notes: 8 effective differential signal dynamic range 9. inl & dnl test limits are adjusted to compensate for the effects of the lrc, dova and dpga stages between teh ext_vins input and the input of the adc.
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 67 imagemos imagemos 15.0 MCM20027 pin definitions figure 20. MCM20027 pin definitions legend: p = v dd g = v ss i = input o = output d = digital a = analog p i x _ o u t 9 c l r c b t s t _ v s e x t _ v i n r c v r e f m c v r e f p v a g v a g r t n v a g r e f clrca avdd avss dvss dvdd init sof strobe top-view 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 sdata 3 0 1 9 2 1 3 3 3 2 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 8 1 6 1 7 2 0 4 4 4 5 4 6 4 7 4 8 1 2 3 4 3 6 4 5 p i x _ o u t 8 p i x _ o u t 7 p i x _ o u t 6 p i x _ o u t 5 d v s s d v d d p i x _ o u t 4 p i x _ o u t 3 p i x _ o u t 2 p i x _ o u t ! p i x _ o u t 0 sclk dvdd dvss vss_pix vdd_pix bias_in avdd avss cvbg extresp extresr e x t _ v i n s a v s s a v d d t s t _ v r sync hclk vclk mclk note: pins 1 & 46 should be pulled down when not in use see section 8.6 for more information see section 8.5 for more information see section 8.4 for more information connect to vdd tn
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 68 imagemos imagemos table 55. MCM20027 pin definitions pin no. pin name description pin type power pin no. pin name description pin type power 1 init sensor initialize i 25 vdd_pix pixel power 2 dvdd digital power p d 26 vss_pix pixel ground 3 dvss digital ground g d 27 dvss digital ground g d 4 avss analog ground g a 28 dvdd digital power p d 5 avdd analog power p a 29 sclk i2c serial clock i/o 6 clrca line rate clamp output o 30 sdata i2c serial data i/o 7 clrcb line rate clamp output o 31 pix_out0 output bit 0 = 1 weight o 8 tst_vr analog test reference output o 32 pix_out1 output bit 1 = 2 weight o 9 tst_vs analog test signal output o 33 pix_out2 output bit 2 = 4 weight o 10 ext_vinr analog test reference input i 34 pix_out3 output bit 3 = 8 weight o 11 ext_vins analog test signal input i 35 pix_out4 output bit 4 = 16 weight o 12 avss analog ground g a 36 dvdd digital power p d 13 avdd analog power p a 37 dvss digital ground g d 14 cvrefm bias reference bottom outpu t o 38 pix_out5 output bit 5 = 32 weight o 15 cvrefp bias reference top output o 39 pix_out6 output bit 6 = 64 weight o 16 vag common mode cap input i 40 pix_out7 output bit 7 = 128 weight o 17 vagretn common mode cap return a 41 pix_out8 output bit 8 = 256 weight o 18 vagref common mode caps input i 42 pix_out9 output bit 9 = 512 weight o 19 extresr tn extres return a 43 mclk master clock i 20 extres external bias resistor input i 44 vclk line sync o 21 cvbg bandgap voltage testpoint 45 hclk pixel sync o 22 avss analog ground g a 46 sync sensor sync signal i 23 avdd analog power p a 47 strobe strobe signal o 24 bias_in pixel row 1046/7 inj bias in i 48 sof start of frame o i input p power g ground o output d digital a analog i/o bidirectional
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 69 imagemos imagemos 16.0 MCM20027 packaging information figure 21. 48 terminal ceramic leadless chip carrier (bottom view) dim min(inches) max(inches) a 0.555 0.572 b 0.525 0.545 c --- 0.09362 d 0.016 0.024 e 0.054 0.068 f 0.075 0.095 g 0.040 bsc h 0.033 0.047 j 0.555 0.572 k 0.525 0.545 r 0.0075 (radius) r1 0.0075 (radius)
motorola, inc. 200 1 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data figure 23. center of the focal plane array with respect to the die cavity (top view) 1 mot inc. m k06k pin 1 48 2 pix_out7 pix_out6 pix_out5 vss vdd pix_out4 pix_out3 pix_out2 pix_out1 15 27 43 pix_out9 pix_out0 pix_out8 sdata sclk vdd vss vss_pix vdd_pix bias_in vdda vssa cvbg extresp vssa mclk vclk hclk sync strobe sof init vdd vss vssa vdda clrca tst_vs ext_vinr ext_vins vssa cvrefm cvrefp vag vssa clrcb vagref tst_vr 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31323334353637383940414244 45 46 47 48 51 53 54 56 58 60 active pixel array center x-axis offset +182m (~7 mil) y-axis offset +1226m (~48 mil) 1716151413121110987 30 29 28 27 26 25 24 23 22 21 20 19 18 42 41 40 39 38 37 36 35 34 33 32 31 pin 1 48 2 47 46 45 44 43 3 4 5 6 vdda 50 52 55 57 59 49 die placement positional tolerance 200um (+/- 4 mil) y-offset: +400m (~16mil) x-offset: +52m (~2mil) notes: 1. dimensions are in inches. 2. interpret dimensions and tolerances per asme y14.5-1994
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 71 imagemos imagemos figure 22. 48 terminal ceramic leadless chip carrier (z-direction view) f - lid seal thickness e - die attach thickness c - die a b g h d j note: the package sketch is representative and does not necessarily reflect exact scale and relative feature sizes. reference notes: 1mil = 25.4um 1mm = 39.37mil dimension description nominal min max nominal min max a glass (thickness) 0.55000 0.50000 0.60000 0.02165 0.01969 0.02362 b cavity (depth) 1.11760 0.99060 1.24460 0.04400 0.03900 0.04900 c die - si (thickness) 0.72500 0.70500 0.74500 0.02854 0.02776 0.02933 d bottom layer (thickness) 0.43180 0.38100 0.48260 0.01700 0.01500 0.01900 e die attach - bondline (thickness) 0.02540 0.01270 0.07620 0.00100 0.00050 0.00300 f glass attach - bondline (thickness) 0.02540 0.00635 0.05080 0.00100 0.00025 0.00200 g imager to lid - outer surface (d) 0.94260 0.67575 1.17770 0.03711 0.02660 0.04637 h imager to lid - inner surface (d) 0.39260 0.17575 0.57770 0.01546 0.00692 0.02274 j imager to seating plane - of pkg 1.18220 1.09870 1.30380 0.04654 0.04326 0.05133 pkg (th - total) 2.12480 1.87795 2.37800 0.08365 0.07393 0.09362 base (th) 1.54940 1.70180 1.39700 0.06100 0.06700 0.05500 metric (mm) english (inches)
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 72 imagemos imagemos 17.0 MCM20027 typical connection below you will find a schematic illustrating a typical connection of an MCM20027 cmos sensor. one can use this as a reference when connecting the sensor with another external device such as an image processor, sdram etc.this schematic also illustrates the connection of the required passives on the sensor. initialize agnd .01uf pixel data 3 +3.3v .01uf gnd .1uf .01uf agnd pixel data 9 pixel data 1 pixel data 2 .01uf pixel data 8 .01uf 4.7/25 agnd i2c_data pixel data 4 pixel data 6 .01uf agnd m20027ib 31 32 33 34 35 38 39 40 41 42 45 3 43 30 26 29 46 5 47 25 1 36 44 20 28 10 22 37 12 6 27 14 2 7 15 48 24 21 19 18 17 16 9 8 11 4 23 13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 hclk dvss mclk sdata vss_pix sclk sync avdd strobe vdd_pix init dvdd vclk extres dvdd ext_vinr avss dvss avss clrca dvss cvrefm dvdd clrcb cvrefp sof bias_in cvbg extresgnd vagref vagretn vag tst_vs tst_vr ext_vins avss avdd avdd pixel data 0 start of frame bead .1uf start data capture avdd dvdd 4.7/25 gnd bead +3.3v .01uf agnd agnd i2c_clk .1uf pixel data 5 gnd gnd .1uf 27k .1uf horizontal sync pixel data 7 .1uf .01uf data valid strobe gnd master clock
motorola, inc. 2001 revision 8.0 - 28 november 2001 : MCM20027 motorola semiconductor technical data 73 imagemos imagemos mfax is a trademark of motorola, inc. how to reach us: usa/europe/locations not listed: motorola literature distribution; japan: nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver colorado 80217. 1-800-441-2447 or 303-675-2140 4-32-1 nishi-gotanda, shinagawa-ku, tokyo, japan. 81-3-5487-8488 mfax tm : rmfax0@email.sps.mot.com -touchtone (602) 244-6609 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, home page: http://motorola.com/sps/ 51 ting kok road, tai po, n.t., hong kong. 852-26629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represent ation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parame ters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all opera ting parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical impla nt into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product coul d create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer sh all indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expense s, and reasonable attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use , even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. electro static discharge warning: this device is sensitive to electrostatic discharge (esd).esd immunity meets human body model (hbm) < 1500 v and machine model (mm) < 150 v additional esd data upon request. when handling this part, proper esd precautions should be followed to avoid exposing the de vice to dis- charges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime..

▲Up To Search▲

Price & Availability of MCM20027

	To Download MCM20027 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .